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authorisiora <none@example.com>2017-11-22 21:08:30 +0000
committerisiora <none@example.com>2017-11-22 21:08:30 +0000
commit71b7be3d452756b85d4d05876a1e1c16ee62558c (patch)
tree5aa9c1168867bfcd12e43ad44c6c43f457d31290
parent1e05a2e1829ee410578522513f9cdfd591e11643 (diff)
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minor changes
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11065 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
index 8450b8bca..e2ae36efd 100644
--- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
@@ -327,7 +327,7 @@ void __mmu_init(void) {
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
/*
- * Invalidate I/D cache
+ * Invalidate L1 I/D cache
* Enable caches and MMU
*/
__set_TTBR0((uint32_t)mmuTable|0x5B);
@@ -336,7 +336,7 @@ void __mmu_init(void) {
__ISB();
/*
- * I cache invalidate and enable
+ * L1 I cache invalidate and enable
*/
pm = __get_SCTLR();
if ((pm & SCTLR_I_Msk) == 0) {
@@ -350,7 +350,7 @@ void __mmu_init(void) {
if ((pm & SCTLR_M_Msk) == 0)
__set_SCTLR(pm | SCTLR_M_Msk);
/*
- * D cache clean, invalidate and enable
+ * L1 D cache clean, invalidate and enable
*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) {