git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1823 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 27 insertions, 33 deletions

diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile
index 36567e197..681c9c790 100644
--- a/demos/ARMCM3-STM32F103-GCC/Makefile
+++ b/demos/ARMCM3-STM32F103-GCC/Makefile
@@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra
 #

 

 # List all default C defines here, like -D_DEBUG=1

-DDEFS = -DSTM32F10X_MD

+DDEFS = -DSTM32F10X_MD -DCORTEX_USE_BASEPRI=TRUE

 

 # List all default ASM defines here, like -D_DEBUG=1

 DADEFS =

diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h
index e627d2302..b844fbffb 100644
--- a/os/ports/GCC/ARMCM3/chcore.h
+++ b/os/ports/GCC/ARMCM3/chcore.h
@@ -131,7 +131,7 @@
  * @brief   BASEPRI user level.

  */

 #ifndef CORTEX_BASEPRI_USER

-#define CORTEX_BASEPRI_USER     CORTEX_PRIORITY_MASK(0)

+#define CORTEX_BASEPRI_USER     0

 #endif

 

 /**

diff --git a/os/ports/GCC/ARMCMx/chcore.c b/os/ports/GCC/ARMCMx/chcore.c
index 78ed6d7ad..908f0b5a6 100644
--- a/os/ports/GCC/ARMCMx/chcore.c
+++ b/os/ports/GCC/ARMCMx/chcore.c
@@ -82,7 +82,7 @@ void _port_switch_from_irq(void) {
   /* Note, saves r4 to make space for the PC.*/

 #if defined(CH_ARCHITECTURE_ARM_v6M)

   asm volatile ("push    {r0, r1, r2, r3, r4}                   \n\t"   \

-                "mrs     r0, XPSR                               \n\t"   \

+                "mrs     r0, APSR                               \n\t"   \

                 "mov     r1, r12                                \n\t"   \

                 "push    {r0, r1, lr}                           \n\t"   \

                 "ldr     r0, =_port_saved_pc                    \n\t"   \

@@ -91,7 +91,7 @@ void _port_switch_from_irq(void) {
                 "str     r0, [sp, #28]");

 #elif defined(CH_ARCHITECTURE_ARM_v7M)

   asm volatile ("push    {r0, r1, r2, r3, r4}                   \n\t"   \

-                "mrs     r0, XPSR                               \n\t"   \

+                "mrs     r0, APSR                               \n\t"   \

                 "push    {r0, r12, lr}                          \n\t"   \

                 "ldr     r0, =_port_saved_pc                    \n\t"   \

                 "ldr     r0, [r0]                               \n\t"   \

@@ -101,25 +101,27 @@ void _port_switch_from_irq(void) {
 

   chSchDoRescheduleI();

 

-  /* Note, the PC is restored alone after re-enabling the interrupts in

-     order to minimize the (very remote and unlikely) possibility that

-     the stack is filled by continuous and saturating interrupts that would

-     not allow that last word to be pulled out of the stack.*/

+  /* Note, the last registers are restored alone after re-enabling the

+     interrupts in order to minimize the (very remote and unlikely)

+     possibility that the stack is filled by continuous and saturating

+     interrupts that would not allow that last words to be pulled out of

+     the stack.*/

 #if defined(CH_ARCHITECTURE_ARM_v6M)

   asm volatile ("pop     {r0, r1, r2}                           \n\t"   \

                 "mov     r12, r1                                \n\t"   \

-                "msr     XPSR, r0                               \n\t"   \

-                "mov     lr, r2                                 \n\t"   \

-                "pop     {r0, r1, r2, r3}                       \n\t"   \

-                "cpsie   i                                      \n\t"   \

-                "pop     {pc}");

+                "msr     APSR, r0                               \n\t"   \

+                "mov     lr, r2");

 #elif defined(CH_ARCHITECTURE_ARM_v7M)

   asm volatile ("pop     {r0, r12, lr}                          \n\t"   \

-                "msr     XPSR, r0                               \n\t"   \

-                "pop     {r0, r1, r2, r3}                       \n\t"   \

-                "cpsie   i                                      \n\t"   \

-                "pop     {pc}");

+                "msr     APSR, r0");

 #endif

+#if CORTEX_USE_BASEPRI

+  asm volatile ("mov     r0, #0                                 \n\t"   \

+                "msr     BASEPRI, r0");

+#else /* !CORTEX_USE_BASEPRI */

+  asm volatile ("cpsie   i");

+#endif /* !CORTEX_USE_BASEPRI */

+  asm volatile ("pop     {r0, r1, r2, r3, pc}");

 }

 

 #if defined(CH_ARCHITECTURE_ARM_v6M)

@@ -189,8 +191,8 @@ void port_switch(Thread *ntp, Thread *otp) {
  */

 void _port_thread_start(void) {

 

-  asm volatile ("cpsie   i                                      \n\t"   \

-                "mov     r0, r5                                 \n\t"   \

+  port_unlock();

+  asm volatile ("mov     r0, r5                                 \n\t"   \

                 "blx     r4                                     \n\t"   \

                 "bl      chThdExit");

 }

diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
index dd7d2897b..e627fcf8f 100644
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ b/os/ports/GCC/ARMCMx/chcore.h
@@ -64,7 +64,8 @@
 /**

  * @brief   Priority masking support.

  */

-#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__)

+#if (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) ||           \

+    defined(__DOXYGEN__)

 #define CORTEX_SUPPORTS_BASEPRI TRUE

 #else

 #define CORTEX_SUPPORTS_BASEPRI FALSE

@@ -153,15 +154,6 @@
 

 #if CORTEX_USE_BASEPRI || defined(__DOXYGEN__)

 /**

- * @brief   BASEPRI user level.

- * @note    This constant is defined only if the @p CORTEX_USE_BASEPRI port

- *          option is enabled.

- */

-#ifndef CORTEX_BASEPRI_USER

-#define CORTEX_BASEPRI_USER     CORTEX_PRIORITY_MASK(0)

-#endif

-

-/**

  * @brief   BASEPRI level within kernel lock.

  * @details Priority levels higher than this one (lower numeric values) are

  *          unaffected by kernel locks and can be classified as fast

@@ -389,9 +381,9 @@ struct context {
 #define PORT_IRQ_EPILOGUE() {                                               \

   chSysLockFromIsr();                                                       \

   if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) {             \

-    register struct cmxctx *ctxp asm ("r3");                                \

+    register struct cmxctx *ctxp;                                           \

                                                                             \

-    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : "r" (ctxp));            \

+    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : );                      \

     _port_saved_pc = ctxp->pc;                                              \

     ctxp->pc = _port_switch_from_irq;                                       \

     return;                                                                 \

@@ -437,7 +429,7 @@ struct context {
  */

 #if CORTEX_USE_BASEPRI

 #define port_unlock() {                                                     \

-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;                   \

+  register uint32_t tmp asm ("r3") = 0;                                     \

   asm volatile ("msr     BASEPRI, %0" : : "r" (tmp));                       \

 }

 #else /* !CORTEX_USE_BASEPRI */

@@ -485,7 +477,7 @@ struct context {
  */

 #if CORTEX_USE_BASEPRI

 #define port_enable() {                                                     \

-  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;                   \

+  register uint32_t tmp asm ("r3") = 0;                                     \

   asm volatile ("msr     BASEPRI, %0                    \n\t"               \

                 "cpsie   i" : : "r" (tmp));                                 \

 }