aboutsummaryrefslogtreecommitdiffstats
path: root/os/ports/GCC/ARMCMx/chcore.c
blob: 78ed6d7adcfb6e1272160a45ef004e293453b53f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/**
 * @file    ARMCMx/chcore.c
 * @brief   ARM Cortex-Mx port code.
 *
 * @addtogroup ARMCMx_CORE
 * @{
 */

#include "ch.h"
#include "nvic.h"

/**
 * @brief   PC register temporary storage.
 */
regarm_t _port_saved_pc;

/**
 * @brief	IRQ nesting counter.
 */
unsigned _port_irq_nesting;

/**
 * @brief   Halts the system.
 * @note    The function is declared as a weak symbol, it is possible
 *          to redefine it in your application code.
 */
#if !defined(__DOXYGEN__)
__attribute__((weak))
#endif
void port_halt(void) {

  port_disable();
  while (TRUE) {
  }
}

/**
 * @brief   System Timer vector.
 * @details This interrupt is used as system tick.
 * @note    The timer must be initialized in the startup code.
 */
CH_IRQ_HANDLER(SysTickVector) {

  CH_IRQ_PROLOGUE();

  chSysLockFromIsr();
  chSysTimerHandlerI();
  chSysUnlockFromIsr();

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   Post-IRQ switch code.
 * @details On entry the stack and the registers are restored by the exception
 *          return, the PC value is stored in @p _port_saved_pc, the interrupts
 *          are disabled.
 */
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void _port_switch_from_irq(void) {
  /* Note, saves r4 to make space for the PC.*/
#if defined(CH_ARCHITECTURE_ARM_v6M)
  asm volatile ("push    {r0, r1, r2, r3, r4}                   \n\t"   \
                "mrs     r0, XPSR                               \n\t"   \
                "mov     r1, r12                                \n\t"   \
                "push    {r0, r1, lr}                           \n\t"   \
                "ldr     r0, =_port_saved_pc                    \n\t"   \
                "ldr     r0, [r0]                               \n\t"   \
                "add 	 r0, r0, #1								\n\t"	\
                "str     r0, [sp, #28]");
#elif defined(CH_ARCHITECTURE_ARM_v7M)
  asm volatile ("push    {r0, r1, r2, r3, r4}                   \n\t"   \
                "mrs     r0, XPSR                               \n\t"   \
                "push    {r0, r12, lr}                          \n\t"   \
                "ldr     r0, =_port_saved_pc                    \n\t"   \
                "ldr     r0, [r0]                               \n\t"   \
                "add     r0, r0, #1                             \n\t"   \
                "str     r0, [sp, #28]");
#endif

  chSchDoRescheduleI();

  /* Note, the PC is restored alone after re-enabling the interrupts in
     order to minimize the (very remote and unlikely) possibility that
     the stack is filled by continuous and saturating interrupts that would
     not allow that last word to be pulled out of the stack.*/
#if defined(CH_ARCHITECTURE_ARM_v6M)
  asm volatile ("pop     {r0, r1, r2}                           \n\t"   \
                "mov     r12, r1                                \n\t"   \
                "msr     XPSR, r0                               \n\t"   \
                "mov     lr, r2                                 \n\t"   \
                "pop     {r0, r1, r2, r3}                       \n\t"   \
                "cpsie   i                                      \n\t"   \
                "pop     {pc}");
#elif defined(CH_ARCHITECTURE_ARM_v7M)
  asm volatile ("pop     {r0, r12, lr}                          \n\t"   \
                "msr     XPSR, r0                               \n\t"   \
                "pop     {r0, r1, r2, r3}                       \n\t"   \
                "cpsie   i                                      \n\t"   \
                "pop     {pc}");
#endif
}

#if defined(CH_ARCHITECTURE_ARM_v6M)
#define PUSH_CONTEXT(sp) {                                              \
  asm volatile ("push    {r4, r5, r6, r7, lr}                   \n\t"   \
                "mov     r4, r8                                 \n\t"   \
                "mov     r5, r9                                 \n\t"   \
                "mov     r6, r10                                \n\t"   \
                "mov     r7, r11                                \n\t"   \
                "push    {r4, r5, r6, r7}");                            \
}

#define POP_CONTEXT(sp) {                                               \
  asm volatile ("pop     {r4, r5, r6, r7}                       \n\t"   \
                "mov     r8, r4                                 \n\t"   \
                "mov     r9, r5                                 \n\t"   \
                "mov     r10, r6                                \n\t"   \
                "mov     r11, r7                                \n\t"   \
                "pop     {r4, r5, r6, r7, pc}" :  : "r" (sp));          \
}
#elif defined(CH_ARCHITECTURE_ARM_v7M)
#define PUSH_CONTEXT(sp) {                                              \
  asm volatile ("push    {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t"); \
}

#define POP_CONTEXT(sp) {                                               \
  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc} \n\t"   \
                :  : "r" (sp));                                         \
}
#endif

/**
 * @brief   Performs a context switch between two threads.
 * @details This is the most critical code in any port, this function
 *          is responsible for the context switch between 2 threads.
 * @note    The implementation of this code affects <b>directly</b> the context
 *          switch performance so optimize here as much as you can.
 *
 * @param[in] ntp       the thread to be switched in
 * @param[in] otp       the thread to be switched out
 */
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void port_switch(Thread *ntp, Thread *otp) {
  register struct intctx *r13 asm ("r13");

  /* Stack overflow check, if enabled.*/
#if CH_DBG_ENABLE_STACK_CHECK
  if ((void *)(r13 - 1) < (void *)(otp + 1))
    asm volatile ("movs    r0, #0                               \n\t"
                  "b       chDbgPanic");
#endif /* CH_DBG_ENABLE_STACK_CHECK */

  PUSH_CONTEXT(r13);

  otp->p_ctx.r13 = r13;
  r13 = ntp->p_ctx.r13;

  POP_CONTEXT(r13);
}

/**
 * @brief   Start a thread by invoking its work function.
 * @details If the work function returns @p chThdExit() is automatically
 *          invoked.
 */
void _port_thread_start(void) {

  asm volatile ("cpsie   i                                      \n\t"   \
                "mov     r0, r5                                 \n\t"   \
                "blx     r4                                     \n\t"   \
                "bl      chThdExit");
}

/** @} */