diff options
| author | pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-02 17:18:51 +0000 |
|---|---|---|
| committer | pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-02 17:18:51 +0000 |
| commit | 26354ec7b79b2127e737ede467db95f91769dd52 (patch) | |
| tree | 65ce64eb7c770f1193b3ecda4d693b0431e80520 | |
| parent | 2c119823065fd4f42d87b6c305025cb8ae972f64 (diff) | |
| download | ChibiOS-26354ec7b79b2127e737ede467db95f91769dd52.tar.gz ChibiOS-26354ec7b79b2127e737ede467db95f91769dd52.tar.bz2 ChibiOS-26354ec7b79b2127e737ede467db95f91769dd52.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5797 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/spc560bc_registry.h | 72 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/xpc560bc.h | 18 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c | 783 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h | 382 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c | 1759 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h | 420 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c | 195 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h | 169 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/Makefile | 121 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/chconf.h | 536 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/halconf.h | 367 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/main.c | 151 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/mcuconf.h | 242 | ||||
| -rw-r--r-- | testhal/SPC560BCxx/ICU-PWM/readme.txt | 27 | ||||
| -rw-r--r-- | testhal/SPC563Mxx/ICU-PWM/readme.txt | 2 | ||||
| -rw-r--r-- | testhal/SPC564Axx/ICU-PWM/readme.txt | 2 |
16 files changed, 5241 insertions, 5 deletions
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h index 79a335075..ebcf5fef5 100644 --- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -89,6 +89,78 @@ #define SPC5_SIUL_NUM_PADSELS 32
#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GLOBAL_PRESCALER)
+
+
+#define SPC5_HAS_EMIOS1 TRUE
+#define SPC5_EMIOS1_PCTL 73
+#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
+#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
+#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
+#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
+#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
+#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
+#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
+#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
+#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
+#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
+#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
+#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
+#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
+#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
+#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
+#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
+#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
+#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
+#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
+#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
+#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
+#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
+#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
+#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
+#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
+#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
+#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
+#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
+
+#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS1_GLOBAL_PRESCALER)
+
/* FlexCAN attributes.*/
#define SPC5_HAS_FLEXCAN0 TRUE
#define SPC5_FLEXCAN0_PCTL 16
diff --git a/os/hal/platforms/SPC560BCxx/xpc560bc.h b/os/hal/platforms/SPC560BCxx/xpc560bc.h index 30cdcb45f..4d7425165 100644 --- a/os/hal/platforms/SPC560BCxx/xpc560bc.h +++ b/os/hal/platforms/SPC560BCxx/xpc560bc.h @@ -1509,7 +1509,11 @@ extern "C" { union {
vuint32_t R;
struct {
- vuint32_t:8;
+ vuint32_t:4;
+ vuint32_t F27:1;
+ vuint32_t F26:1;
+ vuint32_t F25:1;
+ vuint32_t F24:1;
vuint32_t F23:1;
vuint32_t F22:1;
vuint32_t F21:1;
@@ -1540,7 +1544,11 @@ extern "C" { union {
vuint32_t R;
struct {
- vuint32_t:8;
+ vuint32_t:4;
+ vuint32_t OU27:1;
+ vuint32_t OU26:1;
+ vuint32_t OU25:1;
+ vuint32_t OU24:1;
vuint32_t OU23:1;
vuint32_t OU22:1;
vuint32_t OU21:1;
@@ -1571,7 +1579,11 @@ extern "C" { union {
vuint32_t R;
struct {
- vuint32_t:8;
+ vuint32_t:4;
+ vuint32_t CHDIS27:1;
+ vuint32_t CHDIS26:1;
+ vuint32_t CHDIS25:1;
+ vuint32_t CHDIS24:1;
vuint32_t CHDIS23:1;
vuint32_t CHDIS22:1;
vuint32_t CHDIS21:1;
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c new file mode 100644 index 000000000..a8167c69c --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c @@ -0,0 +1,783 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/icu_lld.c
+ * @brief SPC5xx low level ICU driver code.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief ICUD1 driver identifier.
+ * @note The driver ICUD1 allocates the unified channel eMIOS0_CH0
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH0 || defined(__DOXYGEN__)
+ICUDriver ICUD1;
+#endif
+
+/**
+ * @brief ICUD2 driver identifier.
+ * @note The driver ICUD2 allocates the unified channel eMIOS0_CH1
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH1 || defined(__DOXYGEN__)
+ICUDriver ICUD2;
+#endif
+
+/**
+ * @brief ICUD3 driver identifier.
+ * @note The driver ICUD3 allocates the unified channel eMIOS0_CH2
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH2 || defined(__DOXYGEN__)
+ICUDriver ICUD3;
+#endif
+
+/**
+ * @brief ICUD4 driver identifier.
+ * @note The driver ICUD4 allocates the unified channel eMIOS0_CH3
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH3 || defined(__DOXYGEN__)
+ICUDriver ICUD4;
+#endif
+
+/**
+ * @brief ICUD5 driver identifier.
+ * @note The driver ICUD5 allocates the unified channel eMIOS0_CH4
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH4 || defined(__DOXYGEN__)
+ICUDriver ICUD5;
+#endif
+
+/**
+ * @brief ICUD6 driver identifier.
+ * @note The driver ICUD6 allocates the unified channel eMIOS0_CH5
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH5 || defined(__DOXYGEN__)
+ICUDriver ICUD6;
+#endif
+
+/**
+ * @brief ICUD7 driver identifier.
+ * @note The driver ICUD7 allocates the unified channel eMIOS0_CH6
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH6 || defined(__DOXYGEN__)
+ICUDriver ICUD7;
+#endif
+
+/**
+ * @brief ICUD8 driver identifier.
+ * @note The driver ICUD8 allocates the unified channel eMIOS0_CH7
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH7 || defined(__DOXYGEN__)
+ICUDriver ICUD8;
+#endif
+
+/**
+ * @brief ICUD9 driver identifier.
+ * @note The driver ICUD9 allocates the unified channel eMIOS0_CH24
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS0_CH24 || defined(__DOXYGEN__)
+ICUDriver ICUD9;
+#endif
+
+/**
+ * @brief ICUD10 driver identifier.
+ * @note The driver ICUD10 allocates the unified channel eMIOS1_CH24
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS1_CH24 || defined(__DOXYGEN__)
+ICUDriver ICUD10;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Width and Period registers.
+ */
+int16_t width;
+int16_t period;
+
+/**
+ * @brief A2 temp registers.
+ */
+uint16_t A2_1, A2_2, A2_3;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief ICU IRQ handler.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ */
+static void icu_lld_serve_interrupt(ICUDriver *icup) {
+ uint32_t gfr = icup->emiosp->GFR.R;
+
+ if (gfr && (1 << icup->ch_number)) {
+ uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
+
+ if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
+ _icu_isr_invoke_overflow_cb(icup);
+ }
+ if (sr && EMIOSS_FLAG){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
+ if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
+ if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
+ icup->config->period_cb != NULL) {
+ A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ period = A2_3 - A2_1;
+ _icu_isr_invoke_period_cb(icup);
+ A2_1 = A2_3;
+ } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
+ icup->config->width_cb != NULL) {
+ A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ width = A2_2 - A2_1;
+ _icu_isr_invoke_width_cb(icup);
+ }
+ } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
+ if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
+ icup->config->width_cb != NULL) {
+ A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ width = A2_2 - A2_1;
+ _icu_isr_invoke_width_cb(icup);
+ } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
+ icup->config->period_cb != NULL) {
+ A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ period = A2_3 - A2_1;
+ _icu_isr_invoke_period_cb(icup);
+ A2_1 = A2_3;
+ }
+ }
+ }
+ if(sr && EMIOSS_OVR){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
+ }
+
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1
+#if !defined(SPC5_EMIOS0_GFR_F0F1_HANDLER)
+#error "SPC5_EMIOS0_GFR_F0F1_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 0 and 1 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F0F1_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS0_CH0
+ icu_lld_serve_interrupt(&ICUD1);
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH1
+ icu_lld_serve_interrupt(&ICUD2);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 */
+
+#if SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3
+#if !defined(SPC5_EMIOS0_GFR_F2F3_HANDLER)
+#error "SPC5_EMIOS0_GFR_F2F3_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 2 and 3 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F2F3_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS0_CH2
+ icu_lld_serve_interrupt(&ICUD3);
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH3
+ icu_lld_serve_interrupt(&ICUD4);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 */
+
+#if SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5
+#if !defined(SPC5_EMIOS0_GFR_F4F5_HANDLER)
+#error "SPC5_EMIOS0_GFR_F4F5_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 4 and 5 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F4F5_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS0_CH4
+ icu_lld_serve_interrupt(&ICUD5);
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH5
+ icu_lld_serve_interrupt(&ICUD6);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 */
+
+#if SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7
+
+#if !defined(SPC5_EMIOS0_GFR_F6F7_HANDLER)
+#error "SPC5_EMIOS0_GFR_F6F7_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 6 and 7 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F6F7_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS0_CH6
+ icu_lld_serve_interrupt(&ICUD7);
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH7
+ icu_lld_serve_interrupt(&ICUD8);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 */
+
+#if SPC5_ICU_USE_EMIOS0_CH24
+#if !defined(SPC5_EMIOS0_GFR_F24F25_HANDLER)
+#error "SPC5_EMIOS0_GFR_F24F25_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 24 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F24F25_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS0_CH24
+ icu_lld_serve_interrupt(&ICUD9);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
+
+#if SPC5_ICU_USE_EMIOS1_CH24
+#if !defined(SPC5_EMIOS1_GFR_F24F25_HANDLER)
+#error "SPC5_EMIOS1_GFR_F24F25_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 24 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F24F25_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+#if SPC5_ICU_USE_EMIOS1_CH24
+ icu_lld_serve_interrupt(&ICUD10);
+#endif
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ICU driver initialization.
+ *
+ * @notapi
+ */
+void icu_lld_init(void) {
+
+ /* Initialize A2 temp registers.*/
+ A2_1 = 0U;
+ A2_2 = 0U;
+ A2_3 = 0U;
+
+ /* eMIOSx channels initially all not in use.*/
+ reset_emios0_active_channels();
+ reset_emios1_active_channels();
+
+#if SPC5_ICU_USE_EMIOS0_CH0
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD1);
+ ICUD1.emiosp = &EMIOS_0;
+ ICUD1.ch_number = 0U;
+ ICUD1.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
+
+#if SPC5_ICU_USE_EMIOS0_CH1
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD2);
+ ICUD2.emiosp = &EMIOS_0;
+ ICUD2.ch_number = 1U;
+ ICUD2.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
+
+#if SPC5_ICU_USE_EMIOS0_CH2
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD3);
+ ICUD3.emiosp = &EMIOS_0;
+ ICUD3.ch_number = 2U;
+ ICUD3.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
+
+#if SPC5_ICU_USE_EMIOS0_CH3
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD4);
+ ICUD4.emiosp = &EMIOS_0;
+ ICUD4.ch_number = 3U;
+ ICUD4.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
+
+#if SPC5_ICU_USE_EMIOS0_CH4
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD5);
+ ICUD5.emiosp = &EMIOS_0;
+ ICUD5.ch_number = 4U;
+ ICUD5.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
+
+#if SPC5_ICU_USE_EMIOS0_CH5
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD6);
+ ICUD6.emiosp = &EMIOS_0;
+ ICUD6.ch_number = 5U;
+ ICUD6.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
+
+#if SPC5_ICU_USE_EMIOS0_CH6
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD7);
+ ICUD7.emiosp = &EMIOS_0;
+ ICUD7.ch_number = 6U;
+ ICUD7.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
+
+#if SPC5_ICU_USE_EMIOS0_CH7
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD8);
+ ICUD8.emiosp = &EMIOS_0;
+ ICUD8.ch_number = 7U;
+ ICUD8.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
+
+#if SPC5_ICU_USE_EMIOS0_CH24
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD9);
+ ICUD9.emiosp = &EMIOS_0;
+ ICUD9.ch_number = 24U;
+ ICUD9.clock = SPC5_EMIOS0_CLK;
+#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
+
+#if SPC5_ICU_USE_EMIOS1_CH24
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD10);
+ ICUD10.emiosp = &EMIOS_1;
+ ICUD10.ch_number = 24U;
+ ICUD10.clock = SPC5_EMIOS1_CLK;
+#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
+
+#if SPC5_ICU_USE_EMIOS0
+
+ INTC.PSR[SPC5_EMIOS0_GFR_F0F1_NUMBER].R = SPC5_EMIOS0_GFR_F0F1_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F2F3_NUMBER].R = SPC5_EMIOS0_GFR_F2F3_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F4F5_NUMBER].R = SPC5_EMIOS0_GFR_F4F5_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F6F7_NUMBER].R = SPC5_EMIOS0_GFR_F6F7_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F24F25_NUMBER].R = SPC5_EMIOS0_GFR_F24F25_PRIORITY;
+
+#endif
+
+#if SPC5_ICU_USE_EMIOS1
+
+ INTC.PSR[SPC5_EMIOS1_GFR_F24F25_NUMBER].R = SPC5_EMIOS1_GFR_F24F25_PRIORITY;
+
+#endif
+}
+
+/**
+ * @brief Configures and activates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_start(ICUDriver *icup) {
+
+ //uint32_t emios0_active_channels = get_emios0_active_channels();
+ //uint32_t emios1_active_channels = get_emios1_active_channels();
+
+ chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
+ "too many channels");
+
+ chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2",
+ "too many channels");
+
+ if (icup->state == ICU_STOP) {
+ /* Enables the peripheral.*/
+#if SPC5_ICU_USE_EMIOS0_CH0
+ if (&ICUD1 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
+#if SPC5_ICU_USE_EMIOS0_CH1
+ if (&ICUD2 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
+#if SPC5_ICU_USE_EMIOS0_CH2
+ if (&ICUD3 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
+#if SPC5_ICU_USE_EMIOS0_CH3
+ if (&ICUD4 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
+#if SPC5_ICU_USE_EMIOS0_CH4
+ if (&ICUD5 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
+#if SPC5_ICU_USE_EMIOS0_CH5
+ if (&ICUD6 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
+#if SPC5_ICU_USE_EMIOS0_CH6
+ if (&ICUD7 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
+#if SPC5_ICU_USE_EMIOS0_CH7
+ if (&ICUD8 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
+#if SPC5_ICU_USE_EMIOS0_CH24
+ if (&ICUD9 == icup)
+ increase_emios0_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
+#if SPC5_ICU_USE_EMIOS1_CH24
+ if (&ICUD10 == icup)
+ increase_emios1_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
+
+ /* Set eMIOS0 Clock.*/
+#if SPC5_ICU_USE_EMIOS0
+ active_emios0_clock(icup, NULL);
+#endif
+
+ /* Set eMIOS1 Clock.*/
+#if SPC5_ICU_USE_EMIOS1
+ active_emios1_clock(icup, NULL);
+#endif
+
+ }
+ /* Configures the peripheral.*/
+
+ /* Channel enables.*/
+ icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Set clock prescaler and control register.*/
+ uint32_t psc = (icup->clock / icup->config->frequency);
+ chDbgAssert((psc <= 0xFFFF) &&
+ (((psc) * icup->config->frequency) == icup->clock) &&
+ ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
+ "icu_lld_start(), #1", "invalid frequency");
+
+ //icup->emiosp->MCR.B.GPREN = 0;
+ icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
+ icup->emiosp->CH[icup->ch_number].CCR.R |=
+ EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
+ EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
+ icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
+ icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
+ /*
+ if (icup->emiosp == &EMIOS_0) {
+ icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
+ } else if (icup->emiosp == &EMIOS_1) {
+ icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
+ }
+ icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ icup->emiosp->MCR.B.GTBE = 1U;
+ */
+
+ /* Set source polarity.*/
+ if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
+ icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
+ } else {
+ icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
+ }
+
+ /* Direct pointers to the period and width registers in order to make
+ reading data faster from within callbacks.*/
+ icup->pccrp = .
+ icup->wccrp = &width;
+
+ /* Channel disables.*/
+ icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
+
+}
+
+/**
+ * @brief Deactivates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_stop(ICUDriver *icup) {
+
+ //uint32_t emios0_active_channels = get_emios0_active_channels();
+ //uint32_t emios1_active_channels = get_emios1_active_channels();
+
+ chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
+ "too many channels");
+ chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
+ "too many channels");
+
+ if (icup->state == ICU_READY) {
+
+ /* Disables the peripheral.*/
+#if SPC5_ICU_USE_EMIOS0_CH0
+ if (&ICUD1 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
+#if SPC5_ICU_USE_EMIOS0_CH1
+ if (&ICUD2 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
+#if SPC5_ICU_USE_EMIOS0_CH2
+ if (&ICUD3 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
+#if SPC5_ICU_USE_EMIOS0_CH3
+ if (&ICUD4 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
+#if SPC5_ICU_USE_EMIOS0_CH4
+ if (&ICUD5 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
+#if SPC5_ICU_USE_EMIOS0_CH5
+ if (&ICUD6 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
+#if SPC5_ICU_USE_EMIOS0_CH6
+ if (&ICUD7 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
+#if SPC5_ICU_USE_EMIOS0_CH7
+ if (&ICUD8 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
+#if SPC5_ICU_USE_EMIOS0_CH24
+ if (&ICUD9 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
+#if SPC5_ICU_USE_EMIOS1_CH24
+ if (&ICUD10 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios1_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
+
+ /* eMIOS0 clock deactivation.*/
+#if SPC5_ICU_USE_EMIOS0
+ deactive_emios0_clock(icup, NULL);
+#endif
+
+ /* eMIOS1 clock deactivation.*/
+#if SPC5_ICU_USE_EMIOS1
+ deactive_emios1_clock(icup, NULL);
+#endif
+ }
+}
+
+/**
+ * @brief Enables the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_enable(ICUDriver *icup) {
+
+ /* Channel enables.*/
+ /*
+ if (!(icup->emiosp->UCDIS.R && (1 << icup->ch_number))) {
+
+ icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
+ }
+ */
+
+ /* Channel enables.*/
+ icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Active interrupts.*/
+ if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \
+ icup->config->overflow_cb != NULL) {
+ icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
+ }
+
+
+
+ /* Enable Global Time Base.*/
+ /*
+ if (icup->emiosp->MCR.B.GTBE == 0) {
+ icup->emiosp->MCR.B.GTBE = 1U;
+ }
+ */
+
+}
+
+/**
+ * @brief Disables the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_disable(ICUDriver *icup) {
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
+
+ /* Channel disables.*/
+ icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
+
+}
+
+#endif /* HAL_USE_ICU */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h new file mode 100644 index 000000000..31921333c --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h @@ -0,0 +1,382 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/icu_lld.h
+ * @brief SPC5xx low level ICU driver header.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#ifndef _ICU_LLD_H_
+#define _ICU_LLD_H_
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
+/**
+ * @brief ICUD1 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH0) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH0 FALSE
+#endif
+
+/**
+ * @brief ICUD2 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH1) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH1 FALSE
+#endif
+
+/**
+ * @brief ICUD3 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH2) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH2 FALSE
+#endif
+
+/**
+ * @brief ICUD4 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH3) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH3 FALSE
+#endif
+
+/**
+ * @brief ICUD5 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH4) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH4 FALSE
+#endif
+
+/**
+ * @brief ICUD6 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD6 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH5) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH5 FALSE
+#endif
+
+/**
+ * @brief ICUD7 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH6) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH6 FALSE
+#endif
+
+/**
+ * @brief ICUD8 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH7) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH7 FALSE
+#endif
+
+/**
+ * @brief ICUD9 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD9 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS0_CH24) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS0_CH24 FALSE
+#endif
+
+/**
+ * @brief ICUD1 and ICUD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD3 and ICUD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD5 and ICUD6 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD7 and ICUD8 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD9 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7
+#endif
+#endif
+
+#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
+/**
+ * @brief ICUD10 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD10 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS1_CH24) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS1_CH24 FALSE
+#endif
+
+/**
+ * @brief ICUD10 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7
+#endif
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !SPC5_HAS_EMIOS0
+#error "EMIOS0 not present in the selected device"
+#endif
+
+#if !SPC5_HAS_EMIOS1
+#error "EMIOS1 not present in the selected device"
+#endif
+
+#define SPC5_ICU_USE_EMIOS0 (SPC5_ICU_USE_EMIOS0_CH0 || \
+ SPC5_ICU_USE_EMIOS0_CH1 || \
+ SPC5_ICU_USE_EMIOS0_CH2 || \
+ SPC5_ICU_USE_EMIOS0_CH3 || \
+ SPC5_ICU_USE_EMIOS0_CH4 || \
+ SPC5_ICU_USE_EMIOS0_CH5 || \
+ SPC5_ICU_USE_EMIOS0_CH6 || \
+ SPC5_ICU_USE_EMIOS0_CH7 || \
+ SPC5_ICU_USE_EMIOS0_CH24)
+
+#define SPC5_ICU_USE_EMIOS1 SPC5_ICU_USE_EMIOS1_CH24
+
+#if !SPC5_ICU_USE_EMIOS0 && !SPC5_ICU_USE_EMIOS1
+#error "ICU driver activated but no Channels assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ICU driver mode.
+ */
+typedef enum {
+ ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
+ ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
+} icumode_t;
+
+/**
+ * @brief ICU frequency type.
+ */
+typedef uint32_t icufreq_t;
+
+/**
+ * @brief ICU counter type.
+ */
+typedef uint16_t icucnt_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Driver mode.
+ */
+ icumode_t mode;
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ icufreq_t frequency;
+ /**
+ * @brief Callback for pulse width measurement.
+ */
+ icucallback_t width_cb;
+ /**
+ * @brief Callback for cycle period measurement.
+ */
+ icucallback_t period_cb;
+ /**
+ * @brief Callback for timer overflow.
+ */
+ icucallback_t overflow_cb;
+ /* End of the mandatory fields.*/
+} ICUConfig;
+
+/**
+ * @brief Structure representing an ICU driver.
+ */
+struct ICUDriver {
+ /**
+ * @brief Driver state.
+ */
+ icustate_t state;
+ /**
+ * @brief eMIOSx channel number.
+ */
+ uint32_t ch_number;
+ /**
+ * @brief Current configuration data.
+ */
+ const ICUConfig *config;
+ /**
+ * @brief CH Counter clock.
+ */
+ uint32_t clock;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the eMIOSx registers block.
+ */
+ volatile struct EMIOS_tag *emiosp;
+ /**
+ * @brief CCR register used for width capture.
+ */
+ volatile vint16_t *wccrp;
+ /**
+ * @brief CCR register used for period capture.
+ */
+ volatile vint16_t *pccrp;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the width of the latest pulse.
+ * @details The pulse width is defined as number of ticks between the start
+ * edge and the stop edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
+
+/**
+ * @brief Returns the width of the latest cycle.
+ * @details The cycle width is defined as number of ticks between a start
+ * edge and the next start edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_ICU_USE_EMIOS0_CH0 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD1;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH1 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD2;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH2 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD3;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH3 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD4;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH4 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD5;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH5 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD6;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH6 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD7;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH7 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD8;
+#endif
+
+#if SPC5_ICU_USE_EMIOS0_CH24 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD9;
+#endif
+
+#if SPC5_ICU_USE_EMIOS1_CH24 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD10;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void icu_lld_init(void);
+ void icu_lld_start(ICUDriver *icup);
+ void icu_lld_stop(ICUDriver *icup);
+ void icu_lld_enable(ICUDriver *icup);
+ void icu_lld_disable(ICUDriver *icup);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ICU */
+
+#endif /* _ICU_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c new file mode 100644 index 000000000..f353b180a --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c @@ -0,0 +1,1759 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/pwm_lld.c
+ * @brief SPC5xx low level PWM driver code.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the unified channels eMIOS0_CH8 -
+ * eMIOS0_CH15 when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS0_GROUP0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the unified channels eMIOS0_CH16 -
+ * eMIOS0_CH23 when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS0_GROUP1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the unified channels eMIOS1_CH0 -
+ * eMIOS1_CH7 when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS1_GROUP0 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/**
+ * @brief PWMD4 driver identifier.
+ * @note The driver PWMD4 allocates the unified channels eMIOS1_CH8 -
+ * eMIOS1_CH15 when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS1_GROUP1 || defined(__DOXYGEN__)
+PWMDriver PWMD4;
+#endif
+
+/**
+ * @brief PWMD5 driver identifier.
+ * @note The driver PWMD5 allocates the unified channels eMIOS1_CH16 -
+ * eMIOS1_CH23 when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS1_GROUP2 || defined(__DOXYGEN__)
+PWMDriver PWMD5;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief PWM IRQ handler.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ */
+static void pwm_lld_serve_interrupt1(PWMDriver *pwmp, uint32_t index) {
+
+ uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
+ if (sr & EMIOSS_OVFL) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
+ }
+ if (sr & EMIOSS_OVR) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
+ }
+ if (sr & EMIOSS_FLAG) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
+ if (pwmp->config->callback != NULL) {
+ pwmp->config->callback(pwmp);
+ }
+ }
+
+}
+
+static void pwm_lld_serve_interrupt2(PWMDriver *pwmp, uint32_t index) {
+
+ uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
+ if (sr & EMIOSS_OVFL) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
+ }
+ if (sr & EMIOSS_OVR) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
+ }
+ if (sr & EMIOSS_FLAG) {
+ pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
+ if (pwmp->config->channels[index%8U - 1].callback != NULL) {
+ pwmp->config->channels[index%8U - 1].callback(pwmp);
+ }
+ }
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+#if !defined(SPC5_EMIOS0_GFR_F8F9_HANDLER)
+#error "SPC5_EMIOS0_GFR_F8F9_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 8 and 9 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F8F9_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD1.emiosp->GFR.R;
+
+ if (gfr & (1U << 8U)) {
+ pwm_lld_serve_interrupt1(&PWMD1, 8U);
+ }
+ if (gfr & (1U << 9U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 9U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F10F11_HANDLER)
+#error "SPC5_EMIOS0_GFR_F10F11_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 10 and 11 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F10F11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD1.emiosp->GFR.R;
+
+ if (gfr & (1U << 10U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 10U);
+ }
+ if (gfr & (1U << 11U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 11U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F12F13_HANDLER)
+#error "SPC5_EMIOS0_GFR_F12F13_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 12 and 13 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F12F13_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD1.emiosp->GFR.R;
+
+ if (gfr & (1U << 12U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 12U);
+ }
+ if (gfr & (1U << 13U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 13U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F14F15_HANDLER)
+#error "SPC5_EMIOS0_GFR_F14F15_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 14 and 15 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F14F15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD1.emiosp->GFR.R;
+
+ if (gfr && (1U << 14U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 14U);
+ }
+ if (gfr && (1U << 15U)) {
+ pwm_lld_serve_interrupt2(&PWMD1, 15U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+#if !defined(SPC5_EMIOS0_GFR_F16F17_HANDLER)
+#error "SPC5_EMIOS0_GFR_F16F17_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 16 and 17 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F16F17_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD2.emiosp->GFR.R;
+
+ if (gfr && (1U << 16U)) {
+ pwm_lld_serve_interrupt1(&PWMD2, 16U);
+ }
+ if (gfr && (1U << 17U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 17U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F18F19_HANDLER)
+#error "SPC5_EMIOS0_GFR_F18F19_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 18 and 19 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F18F19_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD2.emiosp->GFR.R;
+
+ if (gfr && (1U << 18U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 18U);
+ }
+ if (gfr && (1U << 19U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 19U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F20F21_HANDLER)
+#error "SPC5_EMIOS0_GFR_F20F21_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 20 and 21 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F20F21_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD2.emiosp->GFR.R;
+
+ if (gfr && (1U << 20U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 20U);
+ }
+ if (gfr && (1U << 21U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 21U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS0_GFR_F22F23_HANDLER)
+#error "SPC5_EMIOS0_GFR_F22F23_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS0 Channels 22 and 23 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F22F23_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD2.emiosp->GFR.R;
+
+ if (gfr && (1U << 22U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 22U);
+ }
+ if (gfr && (1U << 23U)) {
+ pwm_lld_serve_interrupt2(&PWMD2, 23U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+#if !defined(SPC5_EMIOS1_GFR_F0F1_HANDLER)
+#error "SPC5_EMIOS1_GFR_F0F1_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 0 and 1 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F0F1_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD3.emiosp->GFR.R;
+
+ if (gfr && (1U << 0)) {
+ pwm_lld_serve_interrupt1(&PWMD3, 0);
+ }
+ if (gfr && (1U << 1U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 1U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F2F3_HANDLER)
+#error "SPC5_EMIOS1_GFR_F2F3_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 2 and 3 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F2F3_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD3.emiosp->GFR.R;
+
+ if (gfr && (1U << 2U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 2U);
+ }
+ if (gfr && (1U << 3U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 3U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F4F5_HANDLER)
+#error "SPC5_EMIOS1_GFR_F4F5_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 4 and 5 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F4F5_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD3.emiosp->GFR.R;
+
+ if (gfr && (1U << 4U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 4U);
+ }
+ if (gfr && (1U << 5U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 5U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F6F7_HANDLER)
+#error "SPC5_EMIOS1_GFR_F6F7_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 6 and 7 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F6F7_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD3.emiosp->GFR.R;
+
+ if (gfr && (1U << 6U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 6U);
+ }
+ if (gfr && (1U << 7U)) {
+ pwm_lld_serve_interrupt2(&PWMD3, 7U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+#if !defined(SPC5_EMIOS1_GFR_F8F9_HANDLER)
+#error "SPC5_EMIOS1_GFR_F8F9_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 8 and 9 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F8F9_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD4.emiosp->GFR.R;
+
+ if (gfr && (1U << 8U)) {
+ pwm_lld_serve_interrupt1(&PWMD4, 8U);
+ }
+ if (gfr && (1U << 9U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 9U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F10F11_HANDLER)
+#error "SPC5_EMIOS1_GFR_F10F11_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 10 and 11 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F10F11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD4.emiosp->GFR.R;
+
+ if (gfr && (1U << 10U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 10U);
+ }
+ if (gfr && (1U << 11U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 11U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F12F13_HANDLER)
+#error "SPC5_EMIOS1_GFR_F12F13_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 12 and 13 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F12F13_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD4.emiosp->GFR.R;
+
+ if (gfr && (1U << 12U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 12U);
+ }
+ if (gfr && (1U << 13U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 13U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F14F15_HANDLER)
+#error "SPC5_EMIOS1_GFR_F14F15_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 14 and 15 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F14F15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD4.emiosp->GFR.R;
+
+ if (gfr && (1U << 14U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 14U);
+ }
+ if (gfr && (1U << 15U)) {
+ pwm_lld_serve_interrupt2(&PWMD4, 15U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+#if !defined(SPC5_EMIOS1_GFR_F16F17_HANDLER)
+#error "SPC5_EMIOS1_GFR_F16F17_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 16 and 17 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F16F17_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD5.emiosp->GFR.R;
+
+ if (gfr && (1U << 16U)) {
+ pwm_lld_serve_interrupt1(&PWMD5, 16U);
+ }
+ if (gfr && (1U << 17U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 17U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F18F19_HANDLER)
+#error "SPC5_EMIOS1_GFR_F18F19_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 18 and 19 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F18F19_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD5.emiosp->GFR.R;
+
+ if (gfr && (1U << 18U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 18U);
+ }
+ if (gfr && (1U << 19U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 19U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F20F21_HANDLER)
+#error "SPC5_EMIOS1_GFR_F20F21_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 20 and 21 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F20F21_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD5.emiosp->GFR.R;
+
+ if (gfr && (1U << 20U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 20U);
+ }
+ if (gfr && (1U << 21U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 21U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_EMIOS1_GFR_F22F23_HANDLER)
+#error "SPC5_EMIOS1_GFR_F22F23_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS1 Channels 22 and 23 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ uint32_t gfr = PWMD5.emiosp->GFR.R;
+
+ if (gfr && (1U << 22U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 22U);
+ }
+ if (gfr && (1U << 23U)) {
+ pwm_lld_serve_interrupt2(&PWMD5, 23U);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+ /* eMIOSx channels initially all not in use.*/
+ reset_emios0_active_channels();
+ reset_emios1_active_channels();
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD1);
+ PWMD1.emiosp = &EMIOS_0;
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD2);
+ PWMD2.emiosp = &EMIOS_0;
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD3);
+ PWMD3.emiosp = &EMIOS_1;
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD4);
+ PWMD4.emiosp = &EMIOS_1;
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD5);
+ PWMD5.emiosp = &EMIOS_1;
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
+
+#if SPC5_PWM_USE_EMIOS0
+
+ INTC.PSR[SPC5_EMIOS0_GFR_F8F9_NUMBER].R = SPC5_EMIOS0_GFR_F8F9_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F10F11_NUMBER].R = SPC5_EMIOS0_GFR_F10F11_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F12F13_NUMBER].R = SPC5_EMIOS0_GFR_F12F13_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F14F15_NUMBER].R = SPC5_EMIOS0_GFR_F14F15_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F16F17_NUMBER].R = SPC5_EMIOS0_GFR_F16F17_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F18F19_NUMBER].R = SPC5_EMIOS0_GFR_F18F19_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F20F21_NUMBER].R = SPC5_EMIOS0_GFR_F20F21_PRIORITY;
+ INTC.PSR[SPC5_EMIOS0_GFR_F22F23_NUMBER].R = SPC5_EMIOS0_GFR_F22F23_PRIORITY;
+
+#endif
+
+#if SPC5_PWM_USE_EMIOS1
+
+ INTC.PSR[SPC5_EMIOS1_GFR_F0F1_NUMBER].R = SPC5_EMIOS1_GFR_F0F1_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F2F3_NUMBER].R = SPC5_EMIOS1_GFR_F2F3_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F4F5_NUMBER].R = SPC5_EMIOS1_GFR_F4F5_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F6F7_NUMBER].R = SPC5_EMIOS1_GFR_F6F7_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F8F9_NUMBER].R = SPC5_EMIOS1_GFR_F8F9_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F10F11_NUMBER].R = SPC5_EMIOS1_GFR_F10F11_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F12F13_NUMBER].R = SPC5_EMIOS1_GFR_F12F13_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F14F15_NUMBER].R = SPC5_EMIOS1_GFR_F14F15_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F16F17_NUMBER].R = SPC5_EMIOS1_GFR_F16F17_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F18F19_NUMBER].R = SPC5_EMIOS1_GFR_F18F19_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F20F21_NUMBER].R = SPC5_EMIOS1_GFR_F20F21_PRIORITY;
+ INTC.PSR[SPC5_EMIOS1_GFR_F22F23_NUMBER].R = SPC5_EMIOS1_GFR_F22F23_PRIORITY;
+
+#endif
+
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+
+ uint32_t psc = 0, i = 0;
+
+ chDbgAssert(get_emios0_active_channels() < 28,
+ "pwm_lld_start(), #1", "too many channels");
+ chDbgAssert(get_emios1_active_channels() < 28,
+ "pwm_lld_start(), #2", "too many channels");
+
+ if (pwmp->state == PWM_STOP) {
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+ increase_emios0_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+ increase_emios0_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+ increase_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+ increase_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+ increase_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
+
+ /* Set eMIOS0 Clock.*/
+#if SPC5_PWM_USE_EMIOS0
+ active_emios0_clock(NULL, pwmp);
+#endif
+
+ /* Set eMIOS1 Clock.*/
+#if SPC5_PWM_USE_EMIOS1
+ active_emios1_clock(NULL, pwmp);
+#endif
+
+ }
+ /* Configures the peripheral.*/
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~1U;
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[0].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ }
+#endif
+
+ /* Set clock prescaler and control register.*/
+ if (pwmp->emiosp == &EMIOS_0) {
+ psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
+ chDbgAssert((psc <= 0xFFFF) &&
+ (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
+ ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
+ "pwm_lld_start(), #1", "invalid frequency");
+ } else if (pwmp->emiosp == &EMIOS_1) {
+ psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
+ chDbgAssert((psc <= 0xFFFF) &&
+ (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
+ ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
+ "pwm_lld_start(), #2", "invalid frequency");
+ }
+
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+
+ pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[8U].CCNTR.R = 1U;
+ pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
+ pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ for (i = 0; i < PWM_CHANNELS; i++) {
+ switch (pwmp->config->channels[i].mode) {
+ case PWM_OUTPUT_DISABLED:
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 9U].CADR.R = 0;
+ pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
+
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
+ pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
+
+ break;
+ }
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 8U);
+
+ }
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+
+ pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[16U].CCNTR.R = 1U;
+ pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
+ pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ for (i = 0; i < PWM_CHANNELS; i++) {
+ switch (pwmp->config->channels[i].mode) {
+ case PWM_OUTPUT_DISABLED:
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 17U].CADR.R = 0;
+ pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
+
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
+ pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
+
+ break;
+ }
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 16U);
+
+ }
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+
+ pwmp->emiosp->CH[0].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[0].CCNTR.R = 1U;
+ pwmp->emiosp->CH[0].CADR.R = pwmp->config->period;
+ pwmp->emiosp->CH[0].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
+ pwmp->emiosp->CH[0].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
+ pwmp->emiosp->CH[0].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[0].CCR.R |= EMIOSC_UCPREN;
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ for (i = 0; i < PWM_CHANNELS; i++) {
+ switch (pwmp->config->channels[i].mode) {
+ case PWM_OUTPUT_DISABLED:
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 1U].CADR.R = 0;
+ pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
+
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 1U].CADR.R = 1U;
+ pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 1U].CCR.R &= ~EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
+
+ break;
+ }
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= 1U;
+
+ }
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+
+ pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[8U].CCNTR.R = 1U;
+ pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
+ pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ for (i = 0; i < PWM_CHANNELS; i++) {
+ switch (pwmp->config->channels[i].mode) {
+ case PWM_OUTPUT_DISABLED:
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 9U].CADR.R = 0;
+ pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
+
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
+ pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
+
+ break;
+ }
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 8U);
+
+ }
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+
+ pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[16U].CCNTR.R = 1U;
+ pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
+ pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ for (i = 0; i < PWM_CHANNELS; i++) {
+ switch (pwmp->config->channels[i].mode) {
+ case PWM_OUTPUT_DISABLED:
+ break;
+ case PWM_OUTPUT_ACTIVE_HIGH:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 17U].CADR.R = 0;
+ pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
+
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
+ pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
+ pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
+
+ /* Set output polarity.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
+
+ /* Set unified channel mode.*/
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
+
+ pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
+
+ break;
+ }
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 16U);
+
+ }
+ }
+#endif
+
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ uint32_t i = 0;
+
+ chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1",
+ "too many channels");
+ chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2",
+ "too many channels");
+
+ if (pwmp->state == PWM_READY) {
+
+ /* Disables the peripheral.*/
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+ /* Reset UC Control Register of group channels.*/
+ for (i = 0; i < 8; i++) {
+ pwmp->emiosp->CH[i + 8U].CCR.R = 0;
+ }
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+ /* Reset UC Control Register of group channels.*/
+ for (i = 0; i < 8; i++) {
+ pwmp->emiosp->CH[i + 16U].CCR.R = 0;
+ }
+ decrease_emios0_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+ /* Reset UC Control Register of group channels.*/
+ for (i = 0; i < 8; i++) {
+ pwmp->emiosp->CH[i].CCR.R = 0;
+ }
+ decrease_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+ /* Reset UC Control Register of group channels.*/
+ for (i = 0; i < 8; i++) {
+ pwmp->emiosp->CH[i + 8U].CCR.R = 0;
+ }
+ decrease_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+ /* Reset UC Control Register of group channels.*/
+ for (i = 0; i < 8; i++) {
+ pwmp->emiosp->CH[i + 16U].CCR.R = 0;
+ }
+ decrease_emios1_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
+
+ /* eMIOS0 clock deactivation.*/
+#if SPC5_PWM_USE_EMIOS0
+ deactive_emios0_clock(NULL, pwmp);
+#endif
+
+ /* eMIOS1 clock deactivation.*/
+#if SPC5_PWM_USE_EMIOS1
+ deactive_emios1_clock(NULL, pwmp);
+#endif
+ }
+}
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+ pwmp->period = period;
+ pwmp->emiosp->CH[8U].CADR.R = period;
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+ pwmp->period = period;
+ pwmp->emiosp->CH[16U].CADR.R = period;
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+ pwmp->period = period;
+ pwmp->emiosp->CH[0].CADR.R = period;
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+ pwmp->period = period;
+ pwmp->emiosp->CH[8U].CADR.R = period;
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+ pwmp->period = period;
+ pwmp->emiosp->CH[16U].CADR.R = period;
+ }
+#endif
+
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ /* Set PWM width.*/
+ pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
+
+ /* Active interrupts.*/
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
+ }
+
+ /* Enables timer base channel if disable.*/
+ if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL ) {
+ pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
+ }
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ /* Set PWM width.*/
+ pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
+
+ /* Active interrupts.*/
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
+ }
+
+ /* Enables timer base channel if disable.*/
+ if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL ) {
+ pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
+ }
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (1U + channel));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ /* Set PWM width.*/
+ pwmp->emiosp->CH[channel + 1U].CBDR.R = width;
+
+
+ /* Active interrupts.*/
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 1U;
+ }
+
+ /* Enables timer base channel if disable.*/
+ if (pwmp->emiosp->UCDIS.R & 1U) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~1U;
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL ) {
+ pwmp->emiosp->CH[0].CCR.B.FEN = 1U;
+ }
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ /* Set PWM width.*/
+ pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
+
+ /* Active interrupts.*/
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
+ }
+
+ /* Enables timer base channel if disable.*/
+ if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL ) {
+ pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
+ }
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
+ EMIOSS_FLAGC;
+
+ /* Set PWM width.*/
+ pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
+
+ /* Active interrupts.*/
+ if (pwmp->config->channels[channel].callback != NULL) {
+ pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
+ }
+
+ /* Enables timer base channel if disable.*/
+ if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL ) {
+ pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
+ }
+ }
+
+ }
+#endif
+
+}
+
+/**
+ * @brief Disables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0
+ if (&PWMD1 == pwmp) {
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
+
+ /* Disable timer base channel if all PWM channels are disabled.*/
+ if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
+ /* Deactive interrupts.*/
+ pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 8U);
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1
+ if (&PWMD2 == pwmp) {
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (channel + 17));
+
+ /* Disable timer base channel if all PWM channels are disabled.*/
+ if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
+ /* Deactive interrupts.*/
+ pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 16U);
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0
+ if (&PWMD3 == pwmp) {
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (channel + 1U));
+
+ /* Disable timer base channel if all PWM channels are disabled.*/
+ if ((pwmp->emiosp->UCDIS.R & 0xFE) == 0xFE) {
+ /* Deactive interrupts.*/
+ pwmp->emiosp->CH[0].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= 1U;
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1
+ if (&PWMD4 == pwmp) {
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
+
+ /* Disable timer base channel if all PWM channels are disabled.*/
+ if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
+ /* Deactive interrupts.*/
+ pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 8U);
+ }
+
+ }
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2
+ if (&PWMD5 == pwmp) {
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << (channel + 17U));
+
+ /* Disable timer base channel if all PWM channels are disabled.*/
+ if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
+ /* Deactive interrupts.*/
+ pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
+
+ /* Disable channel.*/
+ pwmp->emiosp->UCDIS.R |= (1U << 16U);
+ }
+
+ }
+#endif
+
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h new file mode 100644 index 000000000..e2dc403a8 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h @@ -0,0 +1,420 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/pwm_lld.h
+ * @brief SPC5xx low level PWM driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 7
+
+/**
+ * @brief Edge-Aligned PWM functional mode.
+ * @note This is an SPC5-specific setting.
+ */
+#define PWM_ALIGN_EDGE 0x00
+
+/**
+ * @brief Center-Aligned PWM functional mode.
+ * @note This is an SPC5-specific setting.
+ */
+#define PWM_ALIGN_CENTER 0x01
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
+/**
+ * @brief PWMD1 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS0__GROUP0 FALSE
+#endif
+
+/**
+ * @brief PWMD2 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE
+#endif
+
+/**
+ * @brief PWMD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
+#endif
+#endif
+
+#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
+/**
+ * @brief PWMD3 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE
+#endif
+
+/**
+ * @brief PWMD4 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE
+#endif
+
+/**
+ * @brief PWMD5 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE
+#endif
+
+/**
+ * @brief PWMD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
+#endif
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !SPC5_HAS_EMIOS0
+#error "EMIOS0 not present in the selected device"
+#endif
+
+#if !SPC5_HAS_EMIOS1
+#error "EMIOS1 not present in the selected device"
+#endif
+
+#define SPC5_PWM_USE_EMIOS0 (SPC5_PWM_USE_EMIOS0_GROUP0 || \
+ SPC5_PWM_USE_EMIOS0_GROUP1)
+
+#define SPC5_PWM_USE_EMIOS1 (SPC5_PWM_USE_EMIOS1_GROUP0 || \
+ SPC5_PWM_USE_EMIOS1_GROUP1 || \
+ SPC5_PWM_USE_EMIOS1_GROUP2)
+
+#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1
+#error "PWM driver activated but no Channels assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief PWM mode type.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief PWM channel type.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief PWM counter type.
+ */
+typedef uint32_t pwmcnt_t;
+
+/**
+ * @brief PWM driver channel configuration structure.
+ * @note Some architectures may not be able to support the channel mode
+ * or the callback, in this case the fields are ignored.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+ /**
+ * @brief PWM functional mode.
+ */
+ pwmmode_t mode;
+} PWMConfig;
+
+/**
+ * @brief Structure representing an PWM driver.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the eMIOSx registers block.
+ */
+ volatile struct EMIOS_tag *emiosp;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+
+#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD4;
+#endif
+
+#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD5;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c new file mode 100644 index 000000000..20ce38773 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c @@ -0,0 +1,195 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/spc5_emios.c
+ * @brief SPC5xx low level ICU and PWM drivers common code.
+ *
+ * @addtogroup ICU - PWM
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of active eMIOSx Channels.
+ */
+static uint32_t emios0_active_channels;
+static uint32_t emios1_active_channels;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void reset_emios0_active_channels() {
+ emios0_active_channels = 0;
+}
+
+void reset_emios1_active_channels() {
+ emios1_active_channels = 0;
+}
+
+uint32_t get_emios0_active_channels() {
+ return emios0_active_channels;
+}
+
+uint32_t get_emios1_active_channels() {
+ return emios1_active_channels;
+}
+
+void increase_emios0_active_channels() {
+ emios0_active_channels++;
+}
+
+void decrease_emios0_active_channels() {
+ emios0_active_channels--;
+}
+
+void increase_emios1_active_channels() {
+ emios1_active_channels++;
+}
+
+void decrease_emios1_active_channels() {
+ emios1_active_channels--;
+}
+
+void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
+ /* If this is the first Channel activated then the eMIOS0 is enabled.*/
+ if (emios0_active_channels == 1) {
+ halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
+ SPC5_EMIOS0_START_PCTL);
+
+ /* Disable all unified channels.*/
+ if (icup != NULL) {
+ icup->emiosp->MCR.B.GPREN = 0;
+ icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
+ icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ icup->emiosp->MCR.B.GTBE = 1U;
+
+ icup->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ } else if (pwmp != NULL) {
+ pwmp->emiosp->MCR.B.GPREN = 0;
+ pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
+ pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ pwmp->emiosp->MCR.B.GTBE = 1U;
+
+ pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ }
+
+ }
+}
+
+void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
+ /* If this is the first Channel activated then the eMIOS1 is enabled.*/
+ if (emios1_active_channels == 1) {
+ halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
+ SPC5_EMIOS1_START_PCTL);
+
+ /* Disable all unified channels.*/
+ if (icup != NULL) {
+ icup->emiosp->MCR.B.GPREN = 0;
+ icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
+ icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ icup->emiosp->MCR.B.GTBE = 1U;
+
+ icup->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ } else if (pwmp != NULL) {
+ pwmp->emiosp->MCR.B.GPREN = 0;
+ pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
+ pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ pwmp->emiosp->MCR.B.GTBE = 1U;
+
+ pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ }
+
+ }
+}
+
+void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
+ /* If it is the last active channels then the eMIOS0 is disabled.*/
+ if (emios0_active_channels == 0) {
+ if (icup != NULL) {
+ if (icup->emiosp->UCDIS.R == 0) {
+ //icup->emiosp->MCR.B.MDIS = 0;
+ halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
+ SPC5_EMIOS0_STOP_PCTL);
+ }
+ } else if (pwmp != NULL) {
+ if (pwmp->emiosp->UCDIS.R == 0) {
+ //pwmp->emiosp->MCR.B.MDIS = 0;
+ halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
+ SPC5_EMIOS0_STOP_PCTL);
+ }
+ }
+ }
+}
+
+void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
+ /* If it is the last active channels then the eMIOS1 is disabled.*/
+ if (emios1_active_channels == 0) {
+ if (icup != NULL) {
+ if (icup->emiosp->UCDIS.R == 0) {
+ //icup->emiosp->MCR.B.MDIS = 0;
+ halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
+ SPC5_EMIOS1_STOP_PCTL);
+ }
+ } else if (pwmp != NULL) {
+ if (pwmp->emiosp->UCDIS.R == 0) {
+ //pwmp->emiosp->MCR.B.MDIS = 0;
+ halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
+ SPC5_EMIOS1_STOP_PCTL);
+ }
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+
+#endif /* HAL_USE_ICU || HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h new file mode 100644 index 000000000..946db2400 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h @@ -0,0 +1,169 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file eMIOS_v1/spc5_emios.h
+ * @brief SPC5xx low level ICU - PWM driver common header.
+ *
+ * @addtogroup ICU - PWM
+ * @{
+ */
+
+#ifndef _SPC5_EMIOS_H_
+#define _SPC5_EMIOS_H_
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define EMIOSMCR_MDIS (1U << 30U)
+#define EMIOSMCR_FRZ (1U << 29U)
+#define EMIOSMCR_GTBE (1U << 28U)
+#define EMIOSMCR_GPREN (1U << 26U)
+#define EMIOSMCR_GPRE(n) ((n) << 8U)
+
+#define EMIOSC_FREN (1U << 31U)
+#define EMIOSC_UCPRE(n) ((n) << 26U)
+#define EMIOSC_UCPREN (1U << 25U)
+#define EMIOSC_DMA (1U << 24U)
+#define EMIOSC_IF(n) ((n) << 19U)
+#define EMIOSC_FCK (1U << 18U)
+#define EMIOSC_FEN (1U << 17U)
+#define EMIOSC_FORCMA (1U << 13U)
+#define EMIOSC_FORCMB (1U << 12U)
+#define EMIOSC_BSL(n) ((n) << 9U)
+#define EMIOSC_EDSEL (1U << 8U)
+#define EMIOSC_EDPOL (1U << 7U)
+#define EMIOSC_MODE(n) ((n) << 0)
+
+#define EMIOS_BSL_COUNTER_BUS_A 0
+#define EMIOS_BSL_COUNTER_BUS_2 1U
+#define EMIOS_BSL_INTERNAL_COUNTER 3U
+
+#define EMIOS_CCR_MODE_GPIO_IN 0
+#define EMIOS_CCR_MODE_GPIO_OUT 1U
+#define EMIOS_CCR_MODE_SAIC 2U
+#define EMIOS_CCR_MODE_SAOC 3U
+#define EMIOS_CCR_MODE_IPWM 4U
+#define EMIOS_CCR_MODE_IPM 5U
+#define EMIOS_CCR_MODE_DAOC_B_MATCH 6U
+#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7U
+#define EMIOS_CCR_MODE_MC_CMS 16U
+#define EMIOS_CCR_MODE_MC_CME 17U
+#define EMIOS_CCR_MODE_MC_UP_DOWN 18U
+#define EMIOS_CCR_MODE_OPWMT 38U
+#define EMIOS_CCR_MODE_MCB_UP 80U
+#define EMIOS_CCR_MODE_MCB_UP_DOWN 84U
+#define EMIOS_CCR_MODE_OPWFMB 88U
+#define EMIOS_CCR_MODE_OPWMCB_TE 92U
+#define EMIOS_CCR_MODE_OPWMCB_LE 93U
+#define EMIOS_CCR_MODE_OPWMB 96U
+
+#define EMIOSS_OVR (1U << 31U)
+#define EMIOSS_OVRC (1U << 31U)
+#define EMIOSS_OVFL (1U << 15U)
+#define EMIOSS_OVFLC (1U << 15U)
+#define EMIOSS_FLAG (1U << 0)
+#define EMIOSS_FLAGC (1U << 0)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if SPC5_HAS_EMIOS0
+/**
+ * @brief eMIOS0 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EMIOS0_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief eMIOS0 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EMIOS0_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+#endif
+
+#if SPC5_HAS_EMIOS1
+/**
+ * @brief eMIOS1 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EMIOS1_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief eMIOS1 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EMIOS1_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+void reset_emios0_active_channels(void);
+void reset_emios1_active_channels(void);
+uint32_t get_emios0_active_channels(void);
+uint32_t get_emios1_active_channels(void);
+void increase_emios0_active_channels(void);
+void decrease_emios0_active_channels(void);
+void increase_emios1_active_channels(void);
+void decrease_emios1_active_channels(void);
+void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
+void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
+void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
+void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
+
+#endif /* HAL_USE_ICU */
+
+#endif /* _SPC5_EMIOS_H_ */
+
+/** @} */
diff --git a/testhal/SPC560BCxx/ICU-PWM/Makefile b/testhal/SPC560BCxx/ICU-PWM/Makefile new file mode 100644 index 000000000..9e39b8301 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/Makefile @@ -0,0 +1,121 @@ +##############################################################################
+# This file is automatically generated and can be overwritten, do no change
+# this file manually.
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+ USE_VLE = yes
+endif
+
+# Linker options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = out
+
+# Imported source files
+include components/components.mak
+
+# Checks if there is a user mak file in the project directory.
+ifneq ($(wildcard user.mak),)
+ include user.mak
+endif
+
+# Define linker script file here
+LDSCRIPT= application.ld
+
+# C sources here.
+CSRC = $(LIB_C_SRC) \
+ $(APP_C_SRC) \
+ $(U_C_SRC) \
+ ./components/components.c \
+ ./main.c
+
+# C++ sources here.
+CPPSRC = $(LIB_CPP_SRC) \
+ $(APP_CPP_SRC) \
+ $(U_CPP_SRC)
+
+# List ASM source files here
+ASMSRC = $(LIB_ASM_SRC) \
+ $(APP_ASM_SRC) \
+ $(U_ASM_SRC)
+
+INCDIR = $(LIB_INCLUDES) \
+ $(APP_INCLUDES) \
+ ./components
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+TRGT = ppc-vle-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+include C:/SPC5Studio/eclipse/plugins/com.st.tools.spc5.components.platform.spc560bcxx_1.0.0.201305101230/component/lib/rsc/rules.mk
diff --git a/testhal/SPC560BCxx/ICU-PWM/chconf.h b/testhal/SPC560BCxx/ICU-PWM/chconf.h new file mode 100644 index 000000000..db0d97427 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/chconf.h @@ -0,0 +1,536 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+ ---
+
+ A special exception to the GPL can be applied should you wish to distribute
+ a combined work that includes ChibiOS/RT, without being obliged to provide
+ the source code for any proprietary components. See the file exception.txt
+ for full details of how and when the exception can be applied.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES FALSE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC560BCxx/ICU-PWM/halconf.h b/testhal/SPC560BCxx/ICU-PWM/halconf.h new file mode 100644 index 000000000..24462dafd --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/halconf.h @@ -0,0 +1,367 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @name Drivers enable switches
+ */
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM FALSE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU TRUE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name ADC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name CAN driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name I2C driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MAC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MMC_SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SDC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 1
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL_USB driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 64
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+/** @} */
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC560BCxx/ICU-PWM/main.c b/testhal/SPC560BCxx/ICU-PWM/main.c new file mode 100644 index 000000000..11b4a8a23 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/main.c @@ -0,0 +1,151 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+static void pwmpcb(PWMDriver *pwmp) {
+
+ (void)pwmp;
+ palClearPad(PORT_E, PE_LED1);
+
+}
+
+static void pwmc1cb(PWMDriver *pwmp) {
+
+ (void)pwmp;
+ palSetPad(PORT_E, PE_LED1);
+}
+
+static PWMConfig pwmcfg = {
+ 40000, /* 40kHz PWM clock frequency.*/
+ 20000, /* Initial PWM period 0.5s.*/
+ pwmpcb,
+ {
+ {PWM_OUTPUT_ACTIVE_LOW, pwmc1cb},
+ {PWM_OUTPUT_DISABLED, NULL},
+ {PWM_OUTPUT_DISABLED, NULL},
+ {PWM_OUTPUT_DISABLED, NULL},
+ {PWM_OUTPUT_DISABLED, NULL},
+ {PWM_OUTPUT_DISABLED, NULL},
+ {PWM_OUTPUT_DISABLED, NULL}
+ },
+ PWM_ALIGN_EDGE
+};
+
+icucnt_t last_width, last_period;
+
+static void icuwidthcb(ICUDriver *icup) {
+
+ palSetPad(PORT_E, PE_LED2);
+ last_width = icuGetWidth(icup);
+}
+
+static void icuperiodcb(ICUDriver *icup) {
+
+ palClearPad(PORT_E, PE_LED2);
+ last_period = icuGetPeriod(icup);
+}
+
+static ICUConfig icucfg = {
+ ICU_INPUT_ACTIVE_LOW,
+ 40000, /* 40kHz ICU clock frequency.*/
+ icuwidthcb,
+ icuperiodcb,
+ NULL
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ palClearPad(PORT_E, PE_LED4);
+
+ /*
+ * Initializes the PWM driver 1 and ICU driver 1.
+ * GPIOA9 is the PWM channel 0 output.
+ * GPIOA0 is the ICU input.
+ * The two pins have to be externally connected together.
+ */
+ icuStart(&ICUD1, &icucfg);
+ icuEnable(&ICUD1);
+
+ /* Sets A0 alternative function.*/
+ SIU.PCR[0].R = 0b0000010100000100;
+
+ /* Sets A9 alternative function.*/
+ SIU.PCR[9U].R = 0b0000011000000100;
+
+ pwmStart(&PWMD1, &pwmcfg);
+
+ chThdSleepMilliseconds(2000);
+
+ /*
+ * Starts the PWM channel 0 using 75% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes the PWM channel 0 to 50% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes the PWM channel 0 to 25% duty cycle.
+ */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Changes PWM period and the PWM channel 0 to 50% duty cycle.
+ */
+ pwmChangePeriod(&PWMD1, 30000);
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
+ chThdSleepMilliseconds(5000);
+
+ /*
+ * Disables channel 0 and stops the drivers.
+ */
+ pwmDisableChannel(&PWMD1, 0);
+ pwmStop(&PWMD1);
+
+ icuDisable(&ICUD1);
+ icuStop(&ICUD1);
+
+ palClearPad(PORT_E, PE_LED3);
+ palClearPad(PORT_E, PE_LED4);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
diff --git a/testhal/SPC560BCxx/ICU-PWM/mcuconf.h b/testhal/SPC560BCxx/ICU-PWM/mcuconf.h new file mode 100644 index 000000000..010a16b16 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/mcuconf.h @@ -0,0 +1,242 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B/Cxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ */
+
+#define SPC560BCxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT FALSE
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_DISABLE_WATCHDOG TRUE
+#define SPC5_FMPLL0_IDF_VALUE 1
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_XOSCDIV_VALUE 1
+#define SPC5_IRCDIV_VALUE 1
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN_PC0_BITS 0
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_LP_PC0_BITS 0
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 TRUE
+#define SPC5_SERIAL_USE_LINFLEX1 FALSE
+#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_EMIOS0_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
+
+#define SPC5_ICU_USE_EMIOS0_CH0 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH1 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH2 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH3 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH4 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH5 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH6 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH7 TRUE
+#define SPC5_ICU_USE_EMIOS0_CH24 TRUE
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 TRUE
+#define SPC5_PWM_USE_EMIOS0_GROUP1 TRUE
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_EMIOS1_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
+
+#define SPC5_ICU_USE_EMIOS1_CH24 TRUE
+
+#define SPC5_PWM_USE_EMIOS1_GROUP0 TRUE
+#define SPC5_PWM_USE_EMIOS1_GROUP1 TRUE
+#define SPC5_PWM_USE_EMIOS1_GROUP2 TRUE
+
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7
+
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/testhal/SPC560BCxx/ICU-PWM/readme.txt b/testhal/SPC560BCxx/ICU-PWM/readme.txt new file mode 100644 index 000000000..6c64a8d21 --- /dev/null +++ b/testhal/SPC560BCxx/ICU-PWM/readme.txt @@ -0,0 +1,27 @@ +*****************************************************************************
+** ChibiOS/RT HAL - ICU-PWM driver demo for SPC560BCxx. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STMicroelectronics SPC560BCxx microcontroller installed on
+XPC56xx EVB Motherboard.
+
+** The Demo **
+
+The application demonstrates the use of the SPC560BCxx ICU and PWM drivers.
+
+** Board Setup **
+
+Connect PINA0 and PINA9 together.
+
+** Build Procedure **
+
+The demo has been tested using HighTec compiler.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+
+ http://www.st.com
diff --git a/testhal/SPC563Mxx/ICU-PWM/readme.txt b/testhal/SPC563Mxx/ICU-PWM/readme.txt index f56bcf55b..90fcf6d5c 100644 --- a/testhal/SPC563Mxx/ICU-PWM/readme.txt +++ b/testhal/SPC563Mxx/ICU-PWM/readme.txt @@ -1,5 +1,5 @@ *****************************************************************************
-** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx. **
+** ChibiOS/RT HAL - ICU_PWM driver demo for SPC563Mxx. **
*****************************************************************************
** TARGET **
diff --git a/testhal/SPC564Axx/ICU-PWM/readme.txt b/testhal/SPC564Axx/ICU-PWM/readme.txt index f6018c4f3..01668f205 100644 --- a/testhal/SPC564Axx/ICU-PWM/readme.txt +++ b/testhal/SPC564Axx/ICU-PWM/readme.txt @@ -1,5 +1,5 @@ *****************************************************************************
-** ChibiOS/RT HAL - SPI driver demo for SPC564Axx. **
+** ChibiOS/RT HAL - ICU-PWM driver demo for SPC564Axx. **
*****************************************************************************
** TARGET **
|