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/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SPC560B/Cxx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 1...15 Lowest...Highest.
*/
#define SPC560BCxx_MCUCONF
/*
* HAL driver system settings.
*/
#define SPC5_NO_INIT FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_DISABLE_WATCHDOG TRUE
#define SPC5_FMPLL0_IDF_VALUE 1
#define SPC5_FMPLL0_NDIV_VALUE 32
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#define SPC5_XOSCDIV_VALUE 1
#define SPC5_IRCDIV_VALUE 1
#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
SPC5_ME_ME_RUN2 | \
SPC5_ME_ME_RUN3 | \
SPC5_ME_ME_HALT0 | \
SPC5_ME_ME_STOP0 | \
SPC5_ME_ME_STANDBY0)
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#define SPC5_ME_RUN_PC0_BITS 0
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#define SPC5_ME_LP_PC0_BITS 0
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0 | \
SPC5_ME_LP_PC_STANDBY0)
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_PIT0_IRQ_PRIORITY 4
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
* SERIAL driver system settings.
*/
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
#define SPC5_SERIAL_USE_LINFLEX1 FALSE
#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
/*
* ICU-PWM driver system settings.
*/
#define SPC5_EMIOS0_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
#define SPC5_ICU_USE_EMIOS0_CH0 TRUE
#define SPC5_ICU_USE_EMIOS0_CH1 TRUE
#define SPC5_ICU_USE_EMIOS0_CH2 TRUE
#define SPC5_ICU_USE_EMIOS0_CH3 TRUE
#define SPC5_ICU_USE_EMIOS0_CH4 TRUE
#define SPC5_ICU_USE_EMIOS0_CH5 TRUE
#define SPC5_ICU_USE_EMIOS0_CH6 TRUE
#define SPC5_ICU_USE_EMIOS0_CH7 TRUE
#define SPC5_ICU_USE_EMIOS0_CH24 TRUE
#define SPC5_PWM_USE_EMIOS0_GROUP0 TRUE
#define SPC5_PWM_USE_EMIOS0_GROUP1 TRUE
#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7
#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7
#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7
#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7
#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7
#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
#define SPC5_EMIOS1_GLOBAL_PRESCALER 200 /* 8-bit GPRE*/
#define SPC5_ICU_USE_EMIOS1_CH24 TRUE
#define SPC5_PWM_USE_EMIOS1_GROUP0 TRUE
#define SPC5_PWM_USE_EMIOS1_GROUP1 TRUE
#define SPC5_PWM_USE_EMIOS1_GROUP2 TRUE
#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7
#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
SPC5_ME_PCTL_LP(2))
#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
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