STM32 serial driver improvements.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1051 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 36 insertions, 70 deletions

diff --git a/ports/ARMCM3-STM32F103/stm32_serial.c b/ports/ARMCM3-STM32F103/stm32_serial.c
index 109fed212..ab8b364dc 100644
--- a/ports/ARMCM3-STM32F103/stm32_serial.c
+++ b/ports/ARMCM3-STM32F103/stm32_serial.c
@@ -63,13 +63,13 @@ static uint8_t ob3[SERIAL_BUFFERS_SIZE];
 static void SetError(uint16_t sr, FullDuplexDriver *com) {
   dflags_t sts = 0;
 
-  if (sr & SR_ORE)
+  if (sr & USART_SR_ORE)
     sts |= SD_OVERRUN_ERROR;
-  if (sr & SR_PE)
+  if (sr & USART_SR_PE)
     sts |= SD_PARITY_ERROR;
-  if (sr & SR_FE)
+  if (sr & USART_SR_FE)
     sts |= SD_FRAMING_ERROR;
-  if (sr & SR_LBD)
+  if (sr & USART_SR_LBD)
     sts |= SD_BREAK_DETECTED;
   chSysLockFromIsr();
   chFDDAddFlagsI(com, sts);
@@ -84,19 +84,19 @@ static void SetError(uint16_t sr, FullDuplexDriver *com) {
 static void ServeInterrupt(USART_TypeDef *u, FullDuplexDriver *com) {
   uint16_t sr = u->SR;
 
-  if (sr & (SR_ORE | SR_FE | SR_PE | SR_LBD))
+  if (sr & (USART_SR_ORE | USART_SR_FE | USART_SR_PE | USART_SR_LBD))
     SetError(sr, com);
-  if (sr & SR_RXNE) {
+  if (sr & USART_SR_RXNE) {
     chSysLockFromIsr();
     chFDDIncomingDataI(com, u->DR);
     chSysUnlockFromIsr();
   }
-  if (sr & SR_TXE) {
+  if (sr & USART_SR_TXE) {
     chSysLockFromIsr();
     msg_t b = chFDDRequestDataI(com);
     chSysUnlockFromIsr();
     if (b < Q_OK)
-      u->CR1 &= ~CR1_TXEIE;
+      u->CR1 &= ~USART_CR1_TXEIE;
     else
       u->DR = b;
   }
@@ -130,7 +130,7 @@ CH_IRQ_HANDLER(VectorD8) {
 
 static void OutNotify2(void) {
 
-  USART2->CR1 |= CR1_TXEIE;
+  USART2->CR1 |= USART_CR1_TXEIE;
 }
 #endif
 
@@ -175,9 +175,10 @@ void usart_setup(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
   /*
    * Note that some bits are enforced.
    */
-  u->CR1 = cr1 | CR1_UE | CR1_PEIE | CR1_RXNEIE | CR1_TE | CR1_RE;
+  u->CR1 = cr1 | USART_CR1_UE | USART_CR1_PEIE | USART_CR1_RXNEIE |
+           USART_CR1_TE | USART_CR1_RE;
   u->CR2 = cr2;
-  u->CR3 = cr3 | CR3_EIE;
+  u->CR3 = cr3 | USART_CR3_EIE;
 }
 
 /**
@@ -193,27 +194,27 @@ void serial_init(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
 
 #if USE_STM32_USART1
   chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
-  RCC->APB2ENR |= 0x00004000;
+  RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
   usart_setup(USART1, DEFAULT_USART_BITRATE, 0,
-              CR2_STOP1_BITS | CR2_LINEN, 0);
+              USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
   GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004B0;
   NVICEnableVector(USART1_IRQChannel, prio1);
 #endif
 
 #if USE_STM32_USART2
   chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
-  RCC->APB1ENR |= 0x00020000;
+  RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
   usart_setup(USART2, DEFAULT_USART_BITRATE, 0,
-              CR2_STOP1_BITS | CR2_LINEN, 0);
+              USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
   GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004B00;
   NVICEnableVector(USART2_IRQChannel, prio2);
 #endif
 
 #if USE_STM32_USART3
   chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3);
-  RCC->APB1ENR |= 0x00040000;
+  RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
   usart_setup(USART3, DEFAULT_USART_BITRATE, 0,
-              CR2_STOP1_BITS | CR2_LINEN, 0);
+              USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
   GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004B00;
   NVICEnableVector(USART3_IRQChannel, prio3);
 #endif
diff --git a/ports/ARMCM3-STM32F103/stm32_serial.h b/ports/ARMCM3-STM32F103/stm32_serial.h
index ac988db8f..e5b08334c 100644
--- a/ports/ARMCM3-STM32F103/stm32_serial.h
+++ b/ports/ARMCM3-STM32F103/stm32_serial.h
@@ -27,6 +27,18 @@
 #ifndef _STM32_SERIAL_H_

 #define _STM32_SERIAL_H_

 

+/*

+ * Tricks required to make the TRUE/FALSE declaration inside the library

+ * compatible.

+ */

+#ifndef __STM32F10x_MAP_H

+#undef FALSE

+#undef TRUE

+#include "stm32f10x_map.h"

+#define FALSE 0

+#define TRUE (!FALSE)

+#endif

+

 /**

  * @brief Serial buffers size.

  * @details Configuration parameter, you can change the depth of the queue

@@ -76,59 +88,12 @@
 #endif

 

 /*

- * USARTs definitions here.

+ * Extra USARTs definitions here  (missing from the ST header file).

  */

-#define SR_PE                   (1 << 0)    /**< @brief SR PE bit.*/

-#define SR_FE                   (1 << 1)    /**< @brief SR FE bit.*/

-#define SR_NE                   (1 << 2)    /**< @brief SR NE bit.*/

-#define SR_ORE                  (1 << 3)    /**< @brief SR ORE bit.*/

-#define SR_IDLE                 (1 << 4)    /**< @brief SR IDLE bit.*/

-#define SR_RXNE                 (1 << 5)    /**< @brief SR RXNE bit.*/

-#define SR_TC                   (1 << 6)    /**< @brief SR TC bit.*/

-#define SR_TXE                  (1 << 7)    /**< @brief SR TXE bit.*/

-#define SR_LBD                  (1 << 8)    /**< @brief SR LBD bit.*/

-#define SR_CTS                  (1 << 9)    /**< @brief SR CTS bit.*/

-

-#define CR1_SBK                 (1 << 0)    /**< @brief CR1 SBK bit.*/

-#define CR1_RWU                 (1 << 1)    /**< @brief CR1 RWU bit.*/

-#define CR1_RE                  (1 << 2)    /**< @brief CR1 RE bit.*/

-#define CR1_TE                  (1 << 3)    /**< @brief CR1 TE bit.*/

-#define CR1_IDLEIE              (1 << 4)    /**< @brief CR1 IDLEIE bit.*/

-#define CR1_RXNEIE              (1 << 5)    /**< @brief CR1 RXNEIE bit.*/

-#define CR1_TCIE                (1 << 6)    /**< @brief CR1 TCTE bit.*/

-#define CR1_TXEIE               (1 << 7)    /**< @brief CR1 TXEIE bit.*/

-#define CR1_PEIE                (1 << 8)    /**< @brief CR1 PEIE bit.*/

-#define CR1_PS                  (1 << 9)    /**< @brief CR1 PS bit.*/

-#define CR1_PCE                 (1 << 10)   /**< @brief CR1 PCE bit.*/

-#define CR1_WAKE                (1 << 11)   /**< @brief CR1 WAKE bit.*/

-#define CR1_M                   (1 << 12)   /**< @brief CR1 M bit.*/

-#define CR1_UE                  (1 << 13)   /**< @brief CR1 UE bit.*/

-

-#define CR2_ADD_MASK            (15 << 0)   /**< @brief CR2 ADD field mask.*/

-#define CR2_LBDL                (1 << 5)    /**< @brief CR2 LBDL bit.*/

-#define CR2_LBDIE               (1 << 6)    /**< @brief CR2 LBDIE bit.*/

-#define CR2_CBCL                (1 << 8)    /**< @brief CR2 CBCL bit.*/

-#define CR2_CPHA                (1 << 9)    /**< @brief CR2 CPHA bit.*/

-#define CR2_CPOL                (1 << 10)   /**< @brief CR2 CPOL bit.*/

-#define CR2_CLKEN               (1 << 11)   /**< @brief CR2 CLKEN bit.*/

-#define CR2_STOP_MASK           (3 << 12)   /**< @brief CR2 STOP field mask.*/

-#define CR2_STOP1_BITS          (0 << 12)   /**< @brief CR2 1 stop bit value.*/

-#define CR2_STOP0P5_BITS        (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/

-#define CR2_STOP2_BITS          (2 << 12)   /**< @brief CR2 2 stop bit value.*/

-#define CR2_STOP1P5_BITS        (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/

-#define CR2_LINEN               (1 << 14)   /**< @brief CR2 LINEN bit.*/

-

-#define CR3_EIE                 (1 << 0)    /**< @brief CR3 EIE bit.*/

-#define CR3_IREN                (1 << 1)    /**< @brief CR3 IREN bit.*/

-#define CR3_IRLP                (1 << 2)    /**< @brief CR3 IRLP bit.*/

-#define CR3_HDSEL               (1 << 3)    /**< @brief CR3 HDSEL bit.*/

-#define CR3_NACK                (1 << 4)    /**< @brief CR3 NACK bit.*/

-#define CR3_SCEN                (1 << 5)    /**< @brief CR3 SCEN bit.*/

-#define CR3_DMAR                (1 << 6)    /**< @brief CR3 DMAR bit.*/

-#define CR3_DMAT                (1 << 7)    /**< @brief CR3 DMAT bit.*/

-#define CR3_RTSE                (1 << 8)    /**< @brief CR3 RTSE bit.*/

-#define CR3_CTSE                (1 << 9)    /**< @brief CR3 CTSE bit.*/

-#define CR3_CTSIE               (1 << 10)   /**< @brief CR3 CTSIE bit.*/

+#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/

+#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/

+#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/

+#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/

 

 /** @cond never*/

 #if USE_STM32_USART1

diff --git a/readme.txt b/readme.txt
index a8df1dd3d..1ed86bc23 100644
--- a/readme.txt
+++ b/readme.txt
@@ -75,7 +75,7 @@ GNU-Linux-GCC          - ChibiOS/RT simulator for x86 Linux systems, it is
   not supported because its "sparse" registers layout, it would not be

   efficient enough for my taste.

 - Modified the STM32 demo to use the bit definitions in the ST header file,

-  removed the bit definitions in board.h.

+  removed the bit definitions in board.h and stm32_serial.h.

 - Documentation section reorganization and fixes.

 - Changed the STM32 demo stack sizes, it was incorrectly adjusted in version

   1.3.0 but it did not create problems (not a bug).