diff options
Diffstat (limited to 'ports/ARMCM3-STM32F103/stm32_serial.h')
| -rw-r--r-- | ports/ARMCM3-STM32F103/stm32_serial.h | 69 |
1 files changed, 17 insertions, 52 deletions
diff --git a/ports/ARMCM3-STM32F103/stm32_serial.h b/ports/ARMCM3-STM32F103/stm32_serial.h index ac988db8f..e5b08334c 100644 --- a/ports/ARMCM3-STM32F103/stm32_serial.h +++ b/ports/ARMCM3-STM32F103/stm32_serial.h @@ -27,6 +27,18 @@ #ifndef _STM32_SERIAL_H_
#define _STM32_SERIAL_H_
+/*
+ * Tricks required to make the TRUE/FALSE declaration inside the library
+ * compatible.
+ */
+#ifndef __STM32F10x_MAP_H
+#undef FALSE
+#undef TRUE
+#include "stm32f10x_map.h"
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
@@ -76,59 +88,12 @@ #endif
/*
- * USARTs definitions here.
+ * Extra USARTs definitions here (missing from the ST header file).
*/
-#define SR_PE (1 << 0) /**< @brief SR PE bit.*/
-#define SR_FE (1 << 1) /**< @brief SR FE bit.*/
-#define SR_NE (1 << 2) /**< @brief SR NE bit.*/
-#define SR_ORE (1 << 3) /**< @brief SR ORE bit.*/
-#define SR_IDLE (1 << 4) /**< @brief SR IDLE bit.*/
-#define SR_RXNE (1 << 5) /**< @brief SR RXNE bit.*/
-#define SR_TC (1 << 6) /**< @brief SR TC bit.*/
-#define SR_TXE (1 << 7) /**< @brief SR TXE bit.*/
-#define SR_LBD (1 << 8) /**< @brief SR LBD bit.*/
-#define SR_CTS (1 << 9) /**< @brief SR CTS bit.*/
-
-#define CR1_SBK (1 << 0) /**< @brief CR1 SBK bit.*/
-#define CR1_RWU (1 << 1) /**< @brief CR1 RWU bit.*/
-#define CR1_RE (1 << 2) /**< @brief CR1 RE bit.*/
-#define CR1_TE (1 << 3) /**< @brief CR1 TE bit.*/
-#define CR1_IDLEIE (1 << 4) /**< @brief CR1 IDLEIE bit.*/
-#define CR1_RXNEIE (1 << 5) /**< @brief CR1 RXNEIE bit.*/
-#define CR1_TCIE (1 << 6) /**< @brief CR1 TCTE bit.*/
-#define CR1_TXEIE (1 << 7) /**< @brief CR1 TXEIE bit.*/
-#define CR1_PEIE (1 << 8) /**< @brief CR1 PEIE bit.*/
-#define CR1_PS (1 << 9) /**< @brief CR1 PS bit.*/
-#define CR1_PCE (1 << 10) /**< @brief CR1 PCE bit.*/
-#define CR1_WAKE (1 << 11) /**< @brief CR1 WAKE bit.*/
-#define CR1_M (1 << 12) /**< @brief CR1 M bit.*/
-#define CR1_UE (1 << 13) /**< @brief CR1 UE bit.*/
-
-#define CR2_ADD_MASK (15 << 0) /**< @brief CR2 ADD field mask.*/
-#define CR2_LBDL (1 << 5) /**< @brief CR2 LBDL bit.*/
-#define CR2_LBDIE (1 << 6) /**< @brief CR2 LBDIE bit.*/
-#define CR2_CBCL (1 << 8) /**< @brief CR2 CBCL bit.*/
-#define CR2_CPHA (1 << 9) /**< @brief CR2 CPHA bit.*/
-#define CR2_CPOL (1 << 10) /**< @brief CR2 CPOL bit.*/
-#define CR2_CLKEN (1 << 11) /**< @brief CR2 CLKEN bit.*/
-#define CR2_STOP_MASK (3 << 12) /**< @brief CR2 STOP field mask.*/
-#define CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
-#define CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
-#define CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
-#define CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
-#define CR2_LINEN (1 << 14) /**< @brief CR2 LINEN bit.*/
-
-#define CR3_EIE (1 << 0) /**< @brief CR3 EIE bit.*/
-#define CR3_IREN (1 << 1) /**< @brief CR3 IREN bit.*/
-#define CR3_IRLP (1 << 2) /**< @brief CR3 IRLP bit.*/
-#define CR3_HDSEL (1 << 3) /**< @brief CR3 HDSEL bit.*/
-#define CR3_NACK (1 << 4) /**< @brief CR3 NACK bit.*/
-#define CR3_SCEN (1 << 5) /**< @brief CR3 SCEN bit.*/
-#define CR3_DMAR (1 << 6) /**< @brief CR3 DMAR bit.*/
-#define CR3_DMAT (1 << 7) /**< @brief CR3 DMAT bit.*/
-#define CR3_RTSE (1 << 8) /**< @brief CR3 RTSE bit.*/
-#define CR3_CTSE (1 << 9) /**< @brief CR3 CTSE bit.*/
-#define CR3_CTSIE (1 << 10) /**< @brief CR3 CTSIE bit.*/
+#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
+#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
+#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
+#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
/** @cond never*/
#if USE_STM32_USART1
|