diff options
| author | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-08 20:14:13 +0100 |
|---|---|---|
| committer | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-08 20:14:13 +0100 |
| commit | ae7a4d40b84d8afc999691577210696f16e682f6 (patch) | |
| tree | bc7d2dbfeeb6961018da845454232a6d641fcc04 /testhal/STM32/STM32F0xx/qei/mcuconf.h | |
| parent | 32f792087ac05ef8e2c1bafbe5fdaf0f44c302f7 (diff) | |
| download | ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.tar.gz ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.tar.bz2 ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.zip | |
Fixes for STM32F0 testhal
Diffstat (limited to 'testhal/STM32/STM32F0xx/qei/mcuconf.h')
| -rw-r--r-- | testhal/STM32/STM32F0xx/qei/mcuconf.h | 85 |
1 files changed, 49 insertions, 36 deletions
diff --git a/testhal/STM32/STM32F0xx/qei/mcuconf.h b/testhal/STM32/STM32F0xx/qei/mcuconf.h index 6fb24b0..98a9e21 100644 --- a/testhal/STM32/STM32F0xx/qei/mcuconf.h +++ b/testhal/STM32/STM32F0xx/qei/mcuconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,38 +50,33 @@ #define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
-#define STM32_ADCSW STM32_ADCSW_HSI14
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
-#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
+#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
- * ADC driver system settings.
+ * IRQ system settings.
*/
-#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_PRIORITY 2
-#define STM32_ADC_IRQ_PRIORITY 2
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
/*
- * CAN driver system settings.
- */
-#define STM32_CAN_USE_CAN1 FALSE
-#define STM32_CAN_CAN1_IRQ_PRIORITY 11
-
-/*
- * EXT driver system settings.
+ * ADC driver system settings.
*/
-#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
/*
* GPT driver system settings.
@@ -106,9 +101,32 @@ #define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
@@ -130,11 +148,6 @@ #define STM32_PWM_TIM3_IRQ_PRIORITY 3
/*
- * RTC driver system settings.
- */
-#define STM32_RTC_IRQ_PRIORITY 15
-
-/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
@@ -151,6 +164,10 @@ #define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@@ -168,20 +185,16 @@ #define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
- * USB driver system settings.
- */
-#define STM32_USB_USE_USB1 FALSE
-#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
-#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
-#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
-
-/*
* WDG driver system settings.
*/
-#define STM32_WDG_USE_IWDG TRUE
+#define STM32_WDG_USE_IWDG FALSE
/*
* header for community drivers.
|