Merge pull request #81 from awygle/adc

MSP430X ADC12 Support

16 files changed, 1049 insertions, 188 deletions

diff --git a/os/common/ports/MSP430X/chcore.c b/os/common/ports/MSP430X/chcore.c
index 7a8d7f2..b9001b0 100644
--- a/os/common/ports/MSP430X/chcore.c
+++ b/os/common/ports/MSP430X/chcore.c
@@ -32,6 +32,8 @@
 /* Module exported variables.                                                */

 /*===========================================================================*/

 

+bool __msp430x_in_isr;

+

 /*===========================================================================*/

 /* Module local types.                                                       */

 /*===========================================================================*/

@@ -98,6 +100,11 @@ void _port_thread_start(void) {
   asm volatile ("mov R5, R12");

   asm volatile ("call R4");

 #endif

+#if defined(_CHIBIOS_RT_CONF_)

+  chThdExit(MSG_OK);

+#endif

+#if defined(_CHIBIOS_NIL_CONF_)

   chSysHalt(0);

+#endif

 }

 /** @} */

diff --git a/os/common/ports/MSP430X/chcore.h b/os/common/ports/MSP430X/chcore.h
index 09f87c4..9e1efa8 100644
--- a/os/common/ports/MSP430X/chcore.h
+++ b/os/common/ports/MSP430X/chcore.h
@@ -28,6 +28,8 @@
 #include <msp430.h>

 #include <in430.h>

 

+extern bool __msp430x_in_isr;

+

 /*===========================================================================*/

 /* Module constants.                                                         */

 /*===========================================================================*/

@@ -225,21 +227,27 @@ struct port_context {
  * @details This macro must be inserted at the start of all IRQ handlers

  *          enabled to invoke system APIs.

  */

-#define PORT_IRQ_PROLOGUE() 

+#define PORT_IRQ_PROLOGUE() __msp430x_in_isr = true;

 

 /**

  * @brief   IRQ epilogue code.

  * @details This macro must be inserted at the end of all IRQ handlers

  *          enabled to invoke system APIs.

  */

-#define PORT_IRQ_EPILOGUE() chSchRescheduleS()

+#define PORT_IRQ_EPILOGUE() {                                               \

+  __msp430x_in_isr = false;                                                 \

+  _dbg_check_lock();                                                        \

+  if (chSchIsPreemptionRequired())                                          \

+    chSchDoReschedule();                                                    \

+  _dbg_check_unlock();                                                      \

+}

 

 /**

  * @brief   IRQ handler function declaration.

  * @note    @p id can be a function name or a vector number depending on the

  *          port implementation.

  */

-#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id)))                  \

+#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id)))                \

   void ISR_ ## id (void)

 

 /**

@@ -293,7 +301,7 @@ extern "C" {
  * @brief   Port-related initialization code.

  */

 static inline void port_init(void) {

-

+  __msp430x_in_isr = false;

 }

 

 /**

@@ -328,9 +336,7 @@ static inline bool port_irq_enabled(syssts_t sts) {
  * @retval true         running in ISR mode.

  */

 static inline bool port_is_isr_context(void) {

-  /* Efficiency would be enhanced by not doing this, 

-   * because of implementation details */

-  return __get_SR_register() & GIE;

+  return __msp430x_in_isr;

 }

 

 /**

diff --git a/os/hal/boards/EXP430FR5969/board.c b/os/hal/boards/EXP430FR5969/board.c
index ac48ba0..0643cce 100644
--- a/os/hal/boards/EXP430FR5969/board.c
+++ b/os/hal/boards/EXP430FR5969/board.c
@@ -25,11 +25,11 @@
 const PALConfig pal_default_config =

 {

   {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 

-    VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},

+    VAL_IOPORT1_SEL1},

   {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 

-    VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},

+    VAL_IOPORT2_SEL1},

   {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 

-    VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}

+    VAL_IOPORT0_SEL1}

 }; /* Set UART TX pin correctly */

 #endif /* HAL_USE_PAL */

 

diff --git a/os/hal/boards/EXP430FR5969/board.h b/os/hal/boards/EXP430FR5969/board.h
index 97103d3..3abe1cc 100644
--- a/os/hal/boards/EXP430FR5969/board.h
+++ b/os/hal/boards/EXP430FR5969/board.h
@@ -65,8 +65,6 @@
 #define VAL_IOPORT1_REN   0xFCFE

 #define VAL_IOPORT1_SEL0  0x0000

 #define VAL_IOPORT1_SEL1  0x0300

-#define VAL_IOPORT1_IES   0x0000

-#define VAL_IOPORT1_IE    0x0000

 

 /*

  * Port B setup:

@@ -93,8 +91,6 @@
 #define VAL_IOPORT2_REN   0xBDFF

 #define VAL_IOPORT2_SEL0  0x0000

 #define VAL_IOPORT2_SEL1  0x0000

-#define VAL_IOPORT2_IES   0x0000

-#define VAL_IOPORT2_IE    0x0000

 

 /*

  * Port J setup:

@@ -113,8 +109,6 @@
 #define VAL_IOPORT0_REN   0x00CF

 #define VAL_IOPORT0_SEL0  0x0030

 #define VAL_IOPORT0_SEL1  0x0000

-#define VAL_IOPORT0_IES   0x0000

-#define VAL_IOPORT0_IE    0x0000

 

 #if !defined(_FROM_ASM_)

 #ifdef __cplusplus

diff --git a/os/hal/boards/EXP430FR6989/board.c b/os/hal/boards/EXP430FR6989/board.c
index a6836cf..475a2ea 100644
--- a/os/hal/boards/EXP430FR6989/board.c
+++ b/os/hal/boards/EXP430FR6989/board.c
@@ -25,17 +25,17 @@
 const PALConfig pal_default_config =

 {

   {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 

-    VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},

+    VAL_IOPORT1_SEL1},

   {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 

-    VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},

+    VAL_IOPORT2_SEL1},

   {VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0, 

-    VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE},

+    VAL_IOPORT3_SEL1},

   {VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0, 

-    VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE},

+    VAL_IOPORT4_SEL1},

   {VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0, 

-    VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE},

+    VAL_IOPORT5_SEL1},

   {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 

-    VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}

+    VAL_IOPORT0_SEL1}

 }; /* Set UART TX pin correctly */

 #endif /* HAL_USE_PAL */

 

diff --git a/os/hal/boards/EXP430FR6989/board.h b/os/hal/boards/EXP430FR6989/board.h
index 83b8fbb..d5afe29 100644
--- a/os/hal/boards/EXP430FR6989/board.h
+++ b/os/hal/boards/EXP430FR6989/board.h
@@ -69,8 +69,6 @@
 #define VAL_IOPORT1_REN   0xFFFE

 #define VAL_IOPORT1_SEL0  0x0000

 #define VAL_IOPORT1_SEL1  0x0000

-#define VAL_IOPORT1_IES   0x0006

-#define VAL_IOPORT1_IE    0x0006

 

 /*

  * Port B setup:

@@ -97,8 +95,6 @@
 #define VAL_IOPORT2_REN   0xFFCF

 #define VAL_IOPORT2_SEL0  0x0030

 #define VAL_IOPORT2_SEL1  0x0000

-#define VAL_IOPORT2_IES   0x0000

-#define VAL_IOPORT2_IE    0x0000

 

 /*

  * Port C setup:

@@ -125,8 +121,6 @@
 #define VAL_IOPORT3_REN   0xFFFF

 #define VAL_IOPORT3_SEL0  0x0000

 #define VAL_IOPORT3_SEL1  0x0000

-#define VAL_IOPORT3_IES   0x0000

-#define VAL_IOPORT3_IE    0x0000

 

 /*

  * Port D setup:

@@ -153,11 +147,9 @@
 #define VAL_IOPORT4_REN   0xFFFF

 #define VAL_IOPORT4_SEL0  0x0000

 #define VAL_IOPORT4_SEL1  0x0000

-#define VAL_IOPORT4_IES   0x0000

-#define VAL_IOPORT4_IE    0x0000

 

 /*

- * Port D setup:

+ * Port E setup:

  * 

  * P9.0 - BoosterPack BP27        (input pullup)

  * P9.1 - BoosterPack BP28        (input pullup)

@@ -181,8 +173,6 @@
 #define VAL_IOPORT5_REN   0xFF7F

 #define VAL_IOPORT5_SEL0  0x0000

 #define VAL_IOPORT5_SEL1  0x0000

-#define VAL_IOPORT5_IES   0x0000

-#define VAL_IOPORT5_IE    0x0000

 

 /*

  * Port J setup:

@@ -201,8 +191,6 @@
 #define VAL_IOPORT0_REN   0x00CF

 #define VAL_IOPORT0_SEL0  0x0030

 #define VAL_IOPORT0_SEL1  0x0000

-#define VAL_IOPORT0_IES   0x0000

-#define VAL_IOPORT0_IE    0x0000

 

 #if !defined(_FROM_ASM_)

 #ifdef __cplusplus

diff --git a/os/hal/ports/MSP430X/hal_adc_lld.c b/os/hal/ports/MSP430X/hal_adc_lld.c
new file mode 100644
index 0000000..42d3cbe
--- /dev/null
+++ b/os/hal/ports/MSP430X/hal_adc_lld.c
@@ -0,0 +1,354 @@
+/*

+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_adc_lld.c

+ * @brief   MSP430X ADC subsystem low level driver source.

+ *

+ * @addtogroup ADC

+ * @{

+ */

+

+#include "hal.h"

+

+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   ADC1 driver identifier.

+ */

+#if (MSP430X_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)

+ADCDriver ADCD1;

+#endif

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void restart_dma(ADCDriver * adcp) {

+  /* TODO timeouts? */

+  /* Restart DMA transfer */

+  if (adcp->dma.registers == NULL) {

+    /* Acquire a DMA stream because dmaTransfer can be called from ISRs */

+    osalSysLockFromISR();

+    dmaAcquireI(&(adcp->dma), adcp->dma.index);

+    osalSysUnlockFromISR();

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+  else {

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+}

+

+static void dma_callback(void * args) {

+  ADCDriver * adcp = (ADCDriver *)args;

+

+  if (adcp->grpp == NULL)

+    return;

+

+  adcp->count++;

+

+  if (adcp->count == adcp->depth / 2) {

+    /* half-full interrupt */

+    _adc_isr_half_code(adcp);

+  }

+

+  if (adcp->count == adcp->depth) {

+    /* full interrupt */

+

+    /* adc_lld_stop_conversion is called automatically here if needed */

+    _adc_isr_full_code(adcp);

+    /* after isr_full, adcp->grpp is only non-NULL if it's a circular group */

+    if (adcp->grpp) {

+      /* Reset the buffer pointer */

+      adcp->req.dest_addr = adcp->samples;

+

+      restart_dma(adcp);

+

+      /* Reset the count */

+      adcp->count = 0;

+

+      /* Start next sequence */

+      adcp->regs->ctl[0] |= ADC12SC;

+    }

+  }

+  else {

+    /* Advance the buffer pointer */

+    adcp->req.dest_addr = adcp->samples + (adcp->req.size * adcp->count);

+

+    restart_dma(adcp);

+

+    /* Start next sequence */

+    adcp->regs->ctl[0] |= ADC12SC;

+  }

+}

+

+static void populate_tlv(ADCDriver * adcp) {

+  uint8_t * tlv_addr = (uint8_t *)TLV_START;

+

+  while (*tlv_addr != TLV_TAGEND && tlv_addr < (uint8_t *)TLV_END) {

+    if (*tlv_addr == TLV_ADC12CAL) {

+      adcp->adc_cal = (msp430x_adc_cal_t *)(tlv_addr + 2);

+    }

+    else if (*tlv_addr == TLV_REFCAL) {

+      adcp->ref_cal = (msp430x_ref_cal_t *)(tlv_addr + 2);

+    }

+    tlv_addr += (tlv_addr[1] + 2);

+  }

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+PORT_IRQ_HANDLER(ADC12_VECTOR) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  switch (__even_in_range(ADC12IV, ADC12IV_ADC12TOVIFG)) {

+

+  case ADC12IV_ADC12OVIFG: {

+    if (ADCD1.grpp == NULL)

+      break;

+    _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);

+    break;

+  }

+  case ADC12IV_ADC12TOVIFG: {

+    if (ADCD1.grpp == NULL)

+      break;

+    _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);

+    break;

+  }

+  default:

+    osalDbgAssert(false, "unhandled ADC exception");

+    _adc_isr_error_code(&ADCD1, ADC_ERR_UNKNOWN);

+  }

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level ADC driver initialization.

+ *

+ * @notapi

+ */

+void adc_lld_init(void) {

+

+#if MSP430X_ADC_USE_ADC1 == TRUE

+  /* Driver initialization.*/

+  adcObjectInit(&ADCD1);

+  ADCD1.regs = (msp430x_adc_reg_t *)(&ADC12CTL0);

+  populate_tlv(&ADCD1);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the ADC peripheral.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_start(ADCDriver * adcp) {

+

+  if (adcp->state == ADC_STOP) {

+    /* Enables the peripheral.*/

+    adcp->regs->ctl[0] = ADC12ON | ADC12MSC;

+    adcp->regs->ctl[1] =

+        MSP430X_ADC1_PDIV | MSP430X_ADC1_DIV | MSP430X_ADC1_SSEL | ADC12SHP;

+    adcp->regs->ctl[3] = ADC12ICH3MAP | ADC12ICH2MAP | ADC12ICH1MAP |

+                         ADC12ICH0MAP | ADC12TCMAP | ADC12BATMAP;

+    adcp->regs->ier[2] = ADC12TOVIE | ADC12OVIE;

+    adcp->req.trigger  = DMA_TRIGGER_MNEM(ADC12IFG);

+#if MSP430X_ADC_COMPACT_SAMPLES == TRUE

+    adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTBYTE;

+#else

+    adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTWORD;

+#endif

+    adcp->req.addr_mode         = MSP430X_DMA_SRCINCR | MSP430X_DMA_DSTINCR;

+    adcp->req.transfer_mode     = MSP430X_DMA_SINGLE;

+    adcp->req.callback.callback = dma_callback;

+    adcp->req.callback.args     = adcp;

+

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    bool b;

+    if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {

+      b = dmaAcquireI(&adcp->dma, adcp->config->dma_index);

+      osalDbgAssert(!b, "stream already allocated");

+    }

+    else {

+#endif

+      adcp->dma.registers = NULL;

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    }

+#endif

+  }

+  /* Configures the peripheral.*/

+}

+

+/**

+ * @brief   Deactivates the ADC peripheral.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_stop(ADCDriver * adcp) {

+

+  if (adcp->state == ADC_READY) {

+/* Resets the peripheral.*/

+

+/* Disables the peripheral.*/

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+    if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(adcp->dma));

+    }

+#endif

+    adcp->regs->ctl[0] = 0;

+  }

+}

+

+/**

+ * @brief   Starts an ADC conversion.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_start_conversion(ADCDriver * adcp) {

+

+  /* always use sequential transfer mode - this is fine */

+  adcp->regs->ctl[1] |= ADC12CONSEQ0;

+

+  /* set resolution */

+  adcp->regs->ctl[2] |= adcp->grpp->res;

+  /* start from MEM0 */

+  adcp->regs->ctl[3] &= ~(ADC12CSTARTADD_31);

+

+  /* Configure voltage reference */

+  while (REFCTL0 & REFGENBUSY)

+    ;

+  REFCTL0 = adcp->grpp->vref_src;

+

+  for (int i = 0; i < adcp->grpp->num_channels; i++) {

+    osalDbgAssert(adcp->grpp->channels[i] < 32, "invalid channel number");

+    adcp->regs->mctl[i] = adcp->grpp->ref | adcp->grpp->channels[i];

+  }

+

+  adcp->regs->mctl[adcp->grpp->num_channels - 1] |= ADC12EOS;

+

+  adcp->req.source_addr = adcp->regs->mem;

+  adcp->req.dest_addr   = adcp->samples;

+  adcp->req.size        = adcp->grpp->num_channels;

+  adcp->count           = 0;

+

+/* TODO timeouts? */

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {

+    adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);

+  }

+  else {

+    dmaTransfer(&(adcp->dma), &(adcp->req));

+  }

+#else

+  adcp->dma.index       = dmaRequestS(&(adcp->req), TIME_INFINITE);

+#endif

+

+  adcp->regs->ctl[0] |= adcp->grpp->rate | ADC12MSC | ADC12ENC | ADC12SC;

+}

+

+/**

+ * @brief   Stops an ongoing conversion.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object

+ *

+ * @notapi

+ */

+void adc_lld_stop_conversion(ADCDriver * adcp) {

+

+  /* TODO stop DMA transfers here */

+  adcp->regs->ctl[0] &= ~(ADC12ENC | ADC12SC);

+

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {

+#endif

+    if (adcp->dma.registers != NULL) {

+      dmaRelease(&(adcp->dma));

+      adcp->dma.registers = NULL;

+    }

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE

+  }

+#endif

+}

+

+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,

+                                   adcsample_t sample) {

+  uint32_t tmp;

+  uint16_t fact;

+  if (grpp->ref == MSP430X_ADC_VSS_VREF_BUF ||

+      grpp->ref == MSP430X_ADC_VEREF_P_VREF_BUF ||

+      grpp->ref == MSP430X_ADC_VREF_BUF_VCC ||

+      grpp->ref == MSP430X_ADC_VREF_BUF_VEREF_P ||

+      grpp->ref == MSP430X_ADC_VEREF_N_VREF_BUF) {

+    /* Retrieve proper reference correction factor from TLV */

+    fact = (&(ADCD1.ref_cal->CAL_ADC_12VREF_FACTOR))[grpp->vref_src >> 4];

+    /* Calculate corrected value */

+    tmp    = (uint32_t)(sample << 1) * (uint32_t)fact;

+    sample = tmp >> 16;

+  }

+

+  /* Gain correction */

+  fact   = ADCD1.adc_cal->CAL_ADC_GAIN_FACTOR;

+  tmp    = (uint32_t)(sample << 1) * (uint32_t)fact;

+  sample = tmp >> 16;

+

+  /* Offset correction */

+  sample += ADCD1.adc_cal->CAL_ADC_OFFSET;

+

+  return sample;

+}

+

+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp,

+                                 adcsample_t sample) {

+  uint16_t t30;

+  uint16_t t85;

+

+  /* Retrieve proper T = 30 correction value from TLV */

+  t30 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[grpp->vref_src >> 3];

+  /* Retrieve proper T = 85 correction value from TLV */

+  t85 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[(grpp->vref_src >> 3) + 1];

+

+  return ((((int32_t)sample - (int32_t)t30) * (85 - 30)) / (t85 - t30)) + 30;

+}

+

+#endif /* HAL_USE_ADC == TRUE */

+

+/** @} */

diff --git a/os/hal/ports/MSP430X/hal_adc_lld.h b/os/hal/ports/MSP430X/hal_adc_lld.h
new file mode 100644
index 0000000..1cca36b
--- /dev/null
+++ b/os/hal/ports/MSP430X/hal_adc_lld.h
@@ -0,0 +1,516 @@
+/*

+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_adc_lld.h

+ * @brief   MSP430X ADC subsystem low level driver header.

+ *

+ * @addtogroup ADC

+ * @{

+ */

+

+#ifndef HAL_ADC_LLD_H

+#define HAL_ADC_LLD_H

+

+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Sampling rates

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_SHT_4   = 0x0000,

+  MSP430X_ADC_SHT_8   = 0x1100,

+  MSP430X_ADC_SHT_16  = 0x2200,

+  MSP430X_ADC_SHT_32  = 0x3300,

+  MSP430X_ADC_SHT_64  = 0x4400,

+  MSP430X_ADC_SHT_96  = 0x5500,

+  MSP430X_ADC_SHT_128 = 0x6600,

+  MSP430X_ADC_SHT_192 = 0x7700,

+  MSP430X_ADC_SHT_256 = 0x8800,

+  MSP430X_ADC_SHT_384 = 0x9900,

+  MSP430X_ADC_SHT_512 = 0xAA00

+} MSP430XADCSampleRates;

+/** @} */

+

+/**

+ * @name    Resolution

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_RES_8BIT  = 0x0000,

+  MSP430X_ADC_RES_10BIT = 0x0010,

+  MSP430X_ADC_RES_12BIT = 0x0020

+} MSP430XADCResolution;

+/** @} */

+

+/**

+ * @name    References

+ * @{

+ */

+typedef enum {

+  MSP430X_ADC_VSS_VCC             = 0x0000,

+  MSP430X_ADC_VSS_VREF_BUF        = 0x0100,

+  MSP430X_ADC_VSS_VEREF_N         = 0x0200,

+  MSP430X_ADC_VSS_VEREF_P_BUF     = 0x0300,

+  MSP430X_ADC_VSS_VEREF_P         = 0x0400,

+  MSP430X_ADC_VEREF_P_BUF_VCC     = 0x0500,

+  MSP430X_ADC_VEREF_P_VCC         = 0x0600,

+  MSP430X_ADC_VEREF_P_VREF_BUF    = 0x0700,

+  MSP430X_ADC_VREF_BUF_VCC        = 0x0900,

+  MSP430X_ADC_VREF_BUF_VEREF_P    = 0x0B00,

+  MSP430X_ADC_VEREF_N_VCC         = 0x0C00,

+  MSP430X_ADC_VEREF_N_VREF_BUF    = 0x0D00,

+  MSP430X_ADC_VEREF_N_VEREF_P     = 0x0E00,

+  MSP430X_ADC_VEREF_N_VEREF_P_BUF = 0x0F00

+} MSP430XADCReferences;

+

+typedef enum {

+  MSP430X_REF_1V2     = 0x0000,

+  MSP430X_REF_2V0     = 0x0010,

+  MSP430X_REF_2V5     = 0x0020,

+  MSP430X_REF_1V2_EXT = 0x0002,

+  MSP430X_REF_2V0_EXT = 0x0012,

+  MSP430X_REF_2V5_EXT = 0x0022

+} MSP430XREFSources;

+

+#define MSP430X_REF_NONE MSP430X_REF_1V2

+

+/** @} */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    MSP430X configuration options

+ * @{

+ */

+/**

+ * @brief   Stores ADC samples in an 8 bit integer.

+ * @note    10 and 12 bit sampling modes must not be used when this option is

+ *          enabled.

+ */

+#if !defined(MSP430X_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)

+#define MSP430X_ADC_COMPACT_SAMPLES FALSE

+#endif

+

+/**

+ * @brief   ADC1 driver enable switch.

+ * @details If set to @p TRUE the support for ADC1 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(MSP430X_ADC_USE_ADC1) || defined(__DOXYGEN__)

+#define MSP430X_ADC_USE_ADC1 TRUE

+#endif

+

+/**]

+ * @brief   Exclusive DMA enable switch.

+ * @details If set to @p TRUE the support for exclusive DMA is included.

+ * @note    This increases the size of the compiled executable somewhat.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(MSP430X_ADC_EXCLUSIVE_DMA) || defined(__DOXYGEN__)

+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE

+#endif

+

+#if MSP430X_ADC_USE_ADC1

+

+/**

+ * @brief   ADC1 clock source configuration

+ */

+#if !defined(MSP430X_ADC1_CLK_SRC)

+#define MSP430X_ADC1_CLK_SRC MSP430X_MODCLK

+#endif

+

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if MSP430X_ADC_USE_ADC1

+

+#if !defined(__MSP430_HAS_ADC12_B__)

+#error "No ADC present or ADC version not supported"

+#endif

+

+#if (MSP430X_ADC1_CLK_SRC == MSP430X_MODCLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_MODCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_0

+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_ACLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_ACLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_1

+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_MCLK)

+#define MSP$30X_ADC1_CLK_FREQ MSP430X_MCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_2

+#elif (MSP430X_ADC1_CLK_SRC == MSP430SMCLK)

+#define MSP430X_ADC1_CLK_FREQ MSP430X_SMCLK_FREQ

+#define MSP430X_ADC1_SSEL ADC12SSEL_3

+#else

+#error "Invalid ADC1 clock source requested!"

+#endif

+

+#if !defined(MSP430X_ADC1_FREQ)

+#warning "ADC clock frequency not defined - assuming 1 for all dividers"

+#define MSP430X_ADC1_DIV_CALC(x) (x == 1)

+#else

+#define MSP430X_ADC1_DIV_CALC(x)                                               \

+  ((MSP430X_ADC1_CLK_FREQ / x) == MSP430X_ADC1_FREQ)

+#endif

+

+/**

+ * @brief   ADC1 prescaler calculations

+ */

+#if MSP430X_ADC1_DIV_CALC(1)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(2)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_1

+#elif MSP430X_ADC1_DIV_CALC(3)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(4)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(5)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(6)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(7)

+#define MSP430X_ADC1_PDIV ADC12PDIV__1

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(8)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(12)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(16)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_3

+#elif MSP430X_ADC1_DIV_CALC(20)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(24)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(28)

+#define MSP430X_ADC1_PDIV ADC12PDIV__4

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(32)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(64)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_0

+#elif MSP430X_ADC1_DIV_CALC(96)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(128)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_1

+#elif MSP430X_ADC1_DIV_CALC(160)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(192)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_2

+#elif MSP430X_ADC1_DIV_CALC(224)

+#define MSP430X_ADC1_PDIV ADC12PDIV__32

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(256)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_3

+#elif MSP430X_ADC1_DIV_CALC(320)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_4

+#elif MSP430X_ADC1_DIV_CALC(384)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_5

+#elif MSP430X_ADC1_DIV_CALC(448)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_6

+#elif MSP430X_ADC1_DIV_CALC(512)

+#define MSP430X_ADC1_PDIV ADC12PDIV__64

+#define MSP430X_ADC1_DIV ADC12DIV_7

+#else

+#error "MSP430X_ADC1_FREQ not achievable with MSP430X_ADC1_CLK_SRC"

+#endif

+

+#endif /* MSP430X_ADC_USE_ADC1 */

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   ADC sample data type.

+ */

+#if !MSP430X_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)

+typedef uint16_t adcsample_t;

+#else

+typedef uint8_t adcsample_t;

+#endif

+

+/**

+ * @brief   Channels number in a conversion group.

+ */

+typedef uint8_t adc_channels_num_t;

+

+/**

+ * @brief   Possible ADC failure causes.

+ * @note    Error codes are architecture dependent and should not relied

+ *          upon.

+ */

+typedef enum {

+  ADC_ERR_UNKNOWN  = 0, /**< Unknown error has occurred */

+  ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition.    */

+  ADC_ERR_AWD      = 2  /**< Analog watchdog triggered. */

+} adcerror_t;

+

+/**

+ * @brief   Type of a structure representing an ADC driver.

+ */

+typedef struct ADCDriver ADCDriver;

+

+/**

+ * @brief   ADC notification callback type.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the

+ *                      callback

+ * @param[in] buffer    pointer to the most recent samples data

+ * @param[in] n         number of buffer rows available starting from @p buffer

+ */

+typedef void (*adccallback_t)(ADCDriver * adcp, adcsample_t * buffer, size_t n);

+

+/**

+ * @brief   ADC error callback type.

+ *

+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the

+ *                      callback

+ * @param[in] err       ADC error code

+ */

+typedef void (*adcerrorcallback_t)(ADCDriver * adcp, adcerror_t err);

+

+/**

+ * @brief MSP430X ADC register structure.

+ */

+typedef struct {

+  uint16_t ctl[4];

+  uint16_t lo;

+  uint16_t hi;

+  uint16_t ifgr[3];

+  uint16_t ier[3];

+  uint16_t iv;

+  uint16_t padding[3];

+  uint16_t mctl[32];

+  uint16_t mem[32];

+} msp430x_adc_reg_t;

+

+/**

+ * @brief MSP430X ADC calibration structure.

+ */

+typedef struct {

+  uint16_t CAL_ADC_GAIN_FACTOR;

+  uint16_t CAL_ADC_OFFSET;

+  uint16_t CAL_ADC_12T30;

+  uint16_t CAL_ADC_12T85;

+  uint16_t CAL_ADC_20T30;

+  uint16_t CAL_ADC_20T85;

+  uint16_t CAL_ADC_25T30;

+  uint16_t CAL_ADC_25T85;

+} msp430x_adc_cal_t;

+

+/**

+ * @brief MSP430X REF calibration structure.

+ */

+typedef struct {

+  uint16_t CAL_ADC_12VREF_FACTOR;

+  uint16_t CAL_ADC_20VREF_FACTOR;

+  uint16_t CAL_ADC_25VREF_FACTOR;

+} msp430x_ref_cal_t;

+

+/**

+ * @brief   Conversion group configuration structure.

+ * @details This implementation-dependent structure describes a conversion

+ *          operation.

+ * @note    The use of this configuration structure requires knowledge of

+ *          MSP430X ADC cell registers interface, please refer to the MSP430X

+ *          reference manual for details.

+ */

+typedef struct {

+  /**

+   * @brief   Enables the circular buffer mode for the group.

+   */

+  bool circular;

+  /**

+   * @brief   Number of the analog channels belonging to the conversion group.

+   */

+  adc_channels_num_t num_channels;

+  /**

+   * @brief   Callback function associated to the group or @p NULL.

+   */

+  adccallback_t end_cb;

+  /**

+   * @brief   Error callback or @p NULL.

+   */

+  adcerrorcallback_t error_cb;

+  /* End of the mandatory fields.*/

+  /**

+   * @brief   Sequence of analog channels belonging to the conversion group.

+   * @note    Only the first num_channels are valid.

+   */

+  uint8_t channels[32];

+  /**

+   * @brief   Sample resolution

+   */

+  MSP430XADCResolution res;

+  /**

+   * @brief   Sampling time in clock cycles

+   */

+  MSP430XADCSampleRates rate;

+  /**

+   * @brief   Voltage references to use

+   */

+  MSP430XADCReferences ref;

+  /**

+   * @brief   VREF source

+   */

+  MSP430XREFSources vref_src;

+} ADCConversionGroup;

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)

+  /**

+   * @brief The index of the DMA channel.

+   * @note  This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA

+   *        is not used.

+   */

+  uint8_t dma_index;

+#endif

+} ADCConfig;

+

+/**

+ * @brief   Structure representing an ADC driver.

+ */

+struct ADCDriver {

+  /**

+   * @brief Driver state.

+   */

+  adcstate_t state;

+  /**

+   * @brief Current configuration data.

+   */

+  const ADCConfig * config;

+  /**

+   * @brief Current samples buffer pointer or @p NULL.

+   */

+  adcsample_t * samples;

+  /**

+   * @brief Current samples buffer depth or @p 0.

+   */

+  size_t depth;

+  /**

+   * @brief Current conversion group pointer or @p NULL.

+   */

+  const ADCConversionGroup * grpp;

+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief Waiting thread.

+   */

+  thread_reference_t thread;

+#endif

+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief Mutex protecting the peripheral.

+   */

+  mutex_t mutex;

+#endif

+#if defined(ADC_DRIVER_EXT_FIELDS)

+  ADC_DRIVER_EXT_FIELDS

+#endif

+  /* End of the mandatory fields.*/

+  /**

+   * @brief Base address of ADC12_B registers

+   */

+  msp430x_adc_reg_t * regs;

+  /**

+   * @brief DMA request structure

+   */

+  msp430x_dma_req_t req;

+  /**

+   * @brief ADC calibration structure from TLV

+   */

+  msp430x_adc_cal_t * adc_cal;

+  /**

+   * @brief REF calibration structure from TLV

+   */

+  msp430x_ref_cal_t * ref_cal;

+  /**

+   * @brief Count of times DMA callback has been called

+   */

+  uint8_t count;

+  /**

+   * @brief DMA stream

+   */

+  msp430x_dma_ch_t dma;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if (MSP430X_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)

+extern ADCDriver ADCD1;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+void adc_lld_init(void);

+void adc_lld_start(ADCDriver * adcp);

+void adc_lld_stop(ADCDriver * adcp);

+void adc_lld_start_conversion(ADCDriver * adcp);

+void adc_lld_stop_conversion(ADCDriver * adcp);

+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,

+                                   adcsample_t sample);

+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp, adcsample_t sample);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_ADC == TRUE */

+

+#endif /* HAL_ADC_LLD_H */

+

+/** @} */

diff --git a/os/hal/ports/MSP430X/hal_dma_lld.c b/os/hal/ports/MSP430X/hal_dma_lld.c
index 43e1d6c..82bf39f 100644
--- a/os/hal/ports/MSP430X/hal_dma_lld.c
+++ b/os/hal/ports/MSP430X/hal_dma_lld.c
@@ -44,9 +44,8 @@ static msp430x_dma_ch_reg_t * const dma_channels =
     (msp430x_dma_ch_reg_t *)&DMA0CTL;

 

 static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];

-#if CH_CFG_USE_SEMAPHORES

-static semaphore_t dma_lock;

-#endif

+static threads_queue_t dma_queue;

+static unsigned int queue_length;

 

 /*===========================================================================*/

 /* Driver local functions.                                                   */

@@ -88,9 +87,9 @@ PORT_IRQ_HANDLER(DMA_VECTOR) {
   index = (DMAIV >> 1) - 1;

 

   if (index < MSP430X_DMA_CHANNELS) {

-#if CH_CFG_USE_SEMAPHORES

-    chSemSignalI(&dma_lock);

-#endif

+    osalSysLockFromISR();

+    osalThreadDequeueNextI(&dma_queue, MSG_OK);

+    osalSysUnlockFromISR();

 

     msp430x_dma_cb_t * cb = &callbacks[index];

 

@@ -113,9 +112,7 @@ PORT_IRQ_HANDLER(DMA_VECTOR) {
  * @init

  */

 void dmaInit(void) {

-#if CH_CFG_USE_SEMAPHORES

-  chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);

-#endif

+  osalThreadQueueObjectInit(&dma_queue);

 }

 

 /**

@@ -125,134 +122,124 @@ void dmaInit(void) {
  *          semaphores are enabled, the calling thread will sleep until a

  *          channel is available or the request times out. If semaphores are

  *          disabled, the calling thread will busy-wait instead of sleeping.

+ *          

+ *  @sclass

  */

-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {

-/* Check if a DMA channel is available */

-#if CH_CFG_USE_SEMAPHORES

-  msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);

-  if (semresult != MSG_OK)

-    return true;

-#endif

-

-#if !(CH_CFG_USE_SEMAPHORES)

-  systime_t start = chVTGetSystemTimeX();

-

-  do {

-#endif

-    /* Grab the correct DMA channel to use */

-    int i = 0;

-    for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {

-      if (!(dma_channels[i].ctl & DMAEN)) {

-        break;

-      }

-    }

-#if !(CH_CFG_USE_SEMAPHORES)

-    while (chVTTimeElapsedSinceX(start) < timeout)

-      ;

-#endif

-

-#if !(CH_CFG_USE_SEMAPHORES)

-    if (i == MSP430X_DMA_CHANNELS) {

-      return true;

+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout) {

+  

+  osalDbgCheckClassS();

+  

+  /* Check if a DMA channel is available */

+  if (queue_length >= MSP430X_DMA_CHANNELS) {

+    msg_t queueresult = osalThreadEnqueueTimeoutS(&dma_queue, timeout);

+    if (queueresult != MSG_OK)

+      return -1;

+  }

+

+  /* Grab the correct DMA channel to use */

+  int i = 0;

+  for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {

+    if (!(dma_channels[i].ctl & DMAEN)) {

+      break;

     }

-#endif

+  }

+

+  /* Make the request */

+  init_request(request, i);

+  

+  return i;

+}

 

-    /* Make the request */

-    init_request(request, i);

+/**

+ * @brief   Acquires exclusive control of a DMA channel.

+ * @pre     The channel must not be already acquired or an error is returned.

+ * @note    If the channel is in use by the DMA engine, blocks until acquired.

+ * @post    This channel must be interacted with using only the functions

+ *          defined in this module.

+ *

+ * @param[out] channel    The channel handle. Must be pre-allocated.

+ * @param[in]  index      The index of the channel (< MSP430X_DMA_CHANNELS).

+ * @return                The operation status.

+ * @retval false          no error, channel acquired.

+ * @retval true           error, channel already acquired.

+ * 

+ * @iclass

+ */

+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index) {

+  

+  osalDbgCheckClassI();

 

-    return false;

+  /* Is the channel already acquired? */

+  osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");

+  if (dma_channels[index].ctl & DMADT_4) {

+    return true;

   }

 

-  /**

-   * @brief   Acquires exclusive control of a DMA channel.

-   * @pre     The channel must not be already acquired or an error is returned.

-   * @note    If the channel is in use by the DMA engine, blocks until acquired.

-   * @post    This channel must be interacted with using only the functions

-   *          defined in this module.

-   *

-   * @param[out] channel    The channel handle. Must be pre-allocated.

-   * @param[in]  index      The index of the channel (< MSP430X_DMA_CHANNELS).

-   * @return                The operation status.

-   * @retval false          no error, channel acquired.

-   * @retval true           error, channel already acquired.

-   */

-  bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {

-    /* Acquire the channel in an idle mode */

-

-    /* Is the channel already acquired? */

-    osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");

-    if (dma_channels[index].ctl & DMADT_4) {

-      return true;

-    }

+  /* Increment the DMA counter */

+  queue_length++;

 

-/* Increment the DMA counter */

-#if CH_CFG_USE_SEMAPHORES

-    msg_t semresult = chSemWait(&dma_lock);

-    if (semresult != MSG_OK)

-      return true;

-#endif

+  while (dma_channels[index].ctl & DMAEN)

+    ;

 

-    while (dma_channels[index].ctl & DMAEN)

-      ;

+  /* Acquire the channel in an idle mode */

+  dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));

+  dma_channels[index].sz  = 0;

+  dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;

 

-    dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));

-    dma_channels[index].sz  = 0;

-    dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;

+  channel->registers = dma_channels + index;

+  channel->index     = index;

+  channel->cb        = callbacks + index;

+  

+  return false;

+}

 

-    channel->registers = dma_channels + index;

-    channel->index     = index;

-    channel->cb        = callbacks + index;

+/**

+ * @brief   Initiates a DMA transfer operation using an acquired channel.

+ * @pre     The channel must have been acquired using @p dmaAcquire().

+ *

+ * @param[in] channel   pointer to a DMA channel from @p dmaAcquire().

+ * @param[in] request   pointer to a DMA request object.

+ */

+void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {

 

-    return false;

-  }

+  dma_trigger_set(channel->index, request->trigger);

+  /**(channel->ctl) = request->trigger;*/

 

-  /**

-   * @brief   Initiates a DMA transfer operation using an acquired channel.

-   * @pre     The channel must have been acquired using @p dmaAcquire().

-   *

-   * @param[in] channel   pointer to a DMA channel from @p dmaAcquire().

-   * @param[in] request   pointer to a DMA request object.

-   */

-  void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {

-

-    dma_trigger_set(channel->index, request->trigger);

-    /**(channel->ctl) = request->trigger;*/

-

-    channel->cb->callback = request->callback.callback;

-    channel->cb->args     = request->callback.args;

-

-    chSysLock();

-    channel->registers->ctl &= (~DMAEN);

-    channel->registers->sa  = (uintptr_t)request->source_addr;

-    channel->registers->da  = (uintptr_t)request->dest_addr;

-    channel->registers->sz  = request->size;

-    channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |

-                              request->transfer_mode | DMADT_4 | DMAEN |

-                              DMAREQ; /* repeated transfers */

-    chSysUnlock();

-  }

+  channel->cb->callback = request->callback.callback;

+  channel->cb->args     = request->callback.args;

 

-  /**

-   * @brief   Releases exclusive control of a DMA channel.

-   * @details The channel is released from control and returned to the DMA

-   * engine

-   *          pool. Trying to release an unallocated channel is an illegal

-   *          operation and is trapped if assertions are enabled.

-   * @pre     The channel must have been acquired using @p dmaAcquire().

-   * @post    The channel is returned to the DMA engine pool.

-   */

-  void dmaRelease(msp430x_dma_ch_t * channel) {

-

-    osalDbgCheck(channel != NULL);

-

-    /* Release the channel in an idle mode */

-    channel->registers->ctl = DMAABORT;

-

-/* release the DMA counter */

-#if CH_CFG_USE_SEMAPHORES

-    chSemSignal(&dma_lock);

-#endif

-  }

+  channel->registers->ctl &= (~DMAEN);

+  channel->registers->sa  = (uintptr_t)request->source_addr;

+  channel->registers->da  = (uintptr_t)request->dest_addr;

+  channel->registers->sz  = request->size;

+  channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |

+                            request->transfer_mode | DMADT_4 | DMAEN |

+                            DMAREQ; /* repeated transfers */

+}

+

+/**

+ * @brief   Releases exclusive control of a DMA channel.

+ * @details The channel is released from control and returned to the DMA

+ * engine

+ *          pool. Trying to release an unallocated channel is an illegal

+ *          operation and is trapped if assertions are enabled.

+ * @pre     The channel must have been acquired using @p dmaAcquire().

+ * @post    The channel is returned to the DMA engine pool.

+ */

+void dmaRelease(msp430x_dma_ch_t * channel) {

+  syssts_t sts;

+

+  sts = osalSysGetStatusAndLockX();

+  osalDbgCheck(channel != NULL);

+

+  /* Release the channel in an idle mode */

+  channel->registers->ctl = DMAABORT;

+

+  /* release the DMA counter */

+  osalThreadDequeueAllI(&dma_queue, MSG_RESET);

+  queue_length = 0;

+  osalSysRestoreStatusX(sts);

+}

 

 #endif /* HAL_USE_DMA == TRUE */

 

diff --git a/os/hal/ports/MSP430X/hal_dma_lld.h b/os/hal/ports/MSP430X/hal_dma_lld.h
index d1495d2..f558e78 100644
--- a/os/hal/ports/MSP430X/hal_dma_lld.h
+++ b/os/hal/ports/MSP430X/hal_dma_lld.h
@@ -159,8 +159,8 @@ typedef struct {
 extern "C" {

 #endif

 void dmaInit(void);

-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);

-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);

+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout);

+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index);

 void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);

 void dmaRelease(msp430x_dma_ch_t * channel);

 

diff --git a/os/hal/ports/MSP430X/hal_lld.c b/os/hal/ports/MSP430X/hal_lld.c
index 872fe97..812a0cf 100644
--- a/os/hal/ports/MSP430X/hal_lld.c
+++ b/os/hal/ports/MSP430X/hal_lld.c
@@ -82,6 +82,10 @@ void hal_lld_init(void) {
   } while (SFRIFG1 & OFIFG);

   #endif

   CSCTL0_H = 0xFF; /* Lock clock system */

+  

+#if (HAL_USE_DMA == TRUE)

+  dmaInit();

+#endif

 }

 

 /** @} */

diff --git a/os/hal/ports/MSP430X/hal_lld.h b/os/hal/ports/MSP430X/hal_lld.h
index 9549453..62f07e9 100644
--- a/os/hal/ports/MSP430X/hal_lld.h
+++ b/os/hal/ports/MSP430X/hal_lld.h
@@ -25,6 +25,8 @@
 #ifndef _HAL_LLD_H_

 #define _HAL_LLD_H_

 

+#include "hal_dma_lld.h"

+

 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

diff --git a/os/hal/ports/MSP430X/hal_serial_lld.c b/os/hal/ports/MSP430X/hal_serial_lld.c
index 0d9aa1c..feb00ac 100644
--- a/os/hal/ports/MSP430X/hal_serial_lld.c
+++ b/os/hal/ports/MSP430X/hal_serial_lld.c
@@ -374,11 +374,11 @@ PORT_IRQ_HANDLER(USCI_A0_VECTOR) {
     if (oqIsEmptyI(&SD0.oqueue))

       chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);

     UCA0IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -432,11 +432,11 @@ PORT_IRQ_HANDLER(USCI_A1_VECTOR) {
     if (oqIsEmptyI(&SD1.oqueue))

       chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);

     UCA1IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -490,11 +490,11 @@ PORT_IRQ_HANDLER(USCI_A2_VECTOR) {
     if (oqIsEmptyI(&SD2.oqueue))

       chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);

     UCA2IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

@@ -548,11 +548,11 @@ PORT_IRQ_HANDLER(USCI_A3_VECTOR) {
     if (oqIsEmptyI(&SD3.oqueue))

       chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);

     UCA3IE &= ~UCTXCPTIE;

+    osalSysUnlockFromISR();

     break;

 

   default: /* other interrupts */

-    while (1)

-      ;

+    osalDbgAssert(false, "unhandled serial interrupt");

     break;

   }

 

diff --git a/os/hal/ports/MSP430X/hal_spi_lld.c b/os/hal/ports/MSP430X/hal_spi_lld.c
index 70a357e..3a54b1e 100644
--- a/os/hal/ports/MSP430X/hal_spi_lld.c
+++ b/os/hal/ports/MSP430X/hal_spi_lld.c
@@ -104,21 +104,21 @@ static uint16_t dummyrx;
 static void init_transfer(SPIDriver * spip) {

 

 #if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)

-  if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {

-    dmaRequest(&(spip->rx_req), TIME_INFINITE);

+  if (spip->config->dmarx_index >= MSP430X_DMA_CHANNELS) {

+    dmaRequestS(&(spip->rx_req), TIME_INFINITE);

   }

   else {

     dmaTransfer(&(spip->dmarx), &(spip->rx_req));

   }

-  if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {

-    dmaRequest(&(spip->tx_req), TIME_INFINITE);

+  if (spip->config->dmatx_index >= MSP430X_DMA_CHANNELS) {

+    dmaRequestS(&(spip->tx_req), TIME_INFINITE);

   }

   else {

     dmaTransfer(&(spip->dmatx), &(spip->tx_req));

   }

 #else

-  dmaRequest(&(spip->rx_req), TIME_INFINITE);

-  dmaRequest(&(spip->tx_req), TIME_INFINITE);

+  dmaRequestS(&(spip->rx_req), TIME_INFINITE);

+  dmaRequestS(&(spip->tx_req), TIME_INFINITE);

 #endif

 

   *(spip->ifg) |= UCTXIFG;

@@ -325,11 +325,11 @@ void spi_lld_start(SPIDriver * spip) {
     /* Claim DMA streams here */

     bool b;

     if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {

-      b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);

+      b = dmaAcquireI(&(spip->dmatx), spip->config->dmatx_index);

       osalDbgAssert(!b, "stream already allocated");

     }

     if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {

-      b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);

+      b = dmaAcquireI(&(spip->dmarx), spip->config->dmarx_index);

       osalDbgAssert(!b, "stream already allocated");

     }

 #endif /* MSP430X_SPI_EXCLUSIVE_DMA */

@@ -388,10 +388,11 @@ void spi_lld_start(SPIDriver * spip) {
   spip->regs->ctlw0 = UCSWRST;

   spip->regs->brw   = brw;

   spip->regs->ctlw0 =

-      (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |

+      ((spip->config->spi_mode ^ 0x02) << 14) | (spip->config->bit_order << 13) |

       (spip->config->data_size << 12) | (UCMST) |

       ((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);

   *(spip->ifg) = 0;

+  spi_lld_unselect(spip);

 }

 

 /**

@@ -406,8 +407,12 @@ void spi_lld_stop(SPIDriver * spip) {
   if (spip->state == SPI_READY) {

 /* Disables the peripheral.*/

 #if MSP430X_SPI_EXCLUSIVE_DMA == TRUE

-    dmaRelease(&(spip->dmatx));

-    dmaRelease(&(spip->dmarx));

+    if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(spip->dmatx));

+    }

+    if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {

+      dmaRelease(&(spip->dmarx));

+    }

 #endif

     spip->regs->ctlw0 = UCSWRST;

   }

@@ -561,15 +566,12 @@ void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) {
  * @param[in] frame     the data frame to send over the SPI bus

  * @return              The received data frame from the SPI bus.

  */

-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {

-

-  osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");

+uint8_t spi_lld_polled_exchange(SPIDriver * spip, uint8_t frame) {

 

-  while (!(*(spip->ifg) & UCTXIFG))

-    ;

   spip->regs->txbuf = frame;

   while (!(*(spip->ifg) & UCRXIFG))

     ;

+  *(spip->ifg) &= ~(UCRXIFG | UCTXIFG);

   return spip->regs->rxbuf;

 }

 

diff --git a/os/hal/ports/MSP430X/hal_spi_lld.h b/os/hal/ports/MSP430X/hal_spi_lld.h
index ebf14c8..949a8a0 100644
--- a/os/hal/ports/MSP430X/hal_spi_lld.h
+++ b/os/hal/ports/MSP430X/hal_spi_lld.h
@@ -118,7 +118,7 @@
  * @note    This increases the size of the compiled executable somewhat.

  * @note    The default is @p FALSE.

  */

-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)

+#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) || defined(__DOXYGEN__)

 #define MSP430X_SPI_EXCLUSIVE_DMA              FALSE

 #endif

 

@@ -630,7 +630,7 @@ extern "C" {
                         const void *txbuf, void *rxbuf);

   void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);

   void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);

-  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);

+  uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);

 #ifdef __cplusplus

 }

 #endif

diff --git a/os/hal/ports/MSP430X/platform.mk b/os/hal/ports/MSP430X/platform.mk
index 832814b..627a2f0 100644
--- a/os/hal/ports/MSP430X/platform.mk
+++ b/os/hal/ports/MSP430X/platform.mk
@@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \

               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \

               ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \

-              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c 

+              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c \

+              ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_adc_lld.c

 

 # Required include directories

 PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X