[STM32 NAND] Deleted ugly hack with EXTI interrupt instead of NAND one

5 files changed, 9 insertions, 59 deletions

diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
index 05aeceb..0788eb7 100644
--- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
@@ -587,19 +587,14 @@
                                      PIN_OSPEED_100M(GPIOD_MEM_D0) |        \
                                      PIN_OSPEED_100M(GPIOD_MEM_D1))
 
-#if STM32_NAND_USE_EXT_INT
-#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
-#else
-#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
-#endif
 #define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D3) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_PIN2) |       \
                                      PIN_PUPDR_FLOATING(GPIOD_PIN3) |       \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_OE) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_WE) |     \
-                                     NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) |  \
-                                     PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) |   \
+                                     PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\
+                                     PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) |     \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D13) |    \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D14) |    \
                                      PIN_PUPDR_FLOATING(GPIOD_MEM_D15) |    \
@@ -893,21 +888,16 @@
                                      PIN_OSPEED_100M(GPIOG_PIN14) |         \
                                      PIN_OSPEED_100M(GPIOG_PIN15))
 
-#if STM32_NAND_USE_EXT_INT
-#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
-#else
-#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
-#endif
 #define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A11) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A12) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A13) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A14) |    \
                                      PIN_PUPDR_FLOATING(GPIOG_MEM_A15) |    \
-                                     NAND_RB1_PUPDR(GPIOG_NAND_RB1) |       \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) |     \
                                      PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) |   \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
-                                     PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) |   \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) |     \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
                                      PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
                                      PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) |   \
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index 40ad05c..557fa7b 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -125,7 +125,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
       rccResetFSMC();
 #endif
       rccEnableFSMC(FALSE);
-#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+#if HAL_USE_NAND
       nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
 #endif
     }
@@ -153,7 +153,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
     /* Disables the peripheral.*/
 #if STM32_FSMC_USE_FSMC1
     if (&FSMCD1 == fsmcp) {
-#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+#if HAL_USE_NAND
       nvicDisableVector(STM32_FSMC_NUMBER);
 #endif
       rccDisableFSMC(FALSE);
@@ -164,7 +164,6 @@ void fsmc_stop(FSMCDriver *fsmcp) {
   }
 }
 
-#if !STM32_NAND_USE_EXT_INT
 /**
  * @brief   FSMC shared interrupt handler.
  *
@@ -185,7 +184,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
 #endif
   CH_IRQ_EPILOGUE();
 }
-#endif /* !STM32_NAND_USE_EXT_INT */
 
 #endif /* HAL_USE_FSMC */
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index f9d8a60..ba3dafe 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -247,15 +247,6 @@ typedef struct {
 #define STM32_FSMC_USE_FSMC1             FALSE
 #endif
 
-/**
- * @brief   Internal FSMC interrupt enable switch
- * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC.
- *          You have to use EXTI module instead to workaround this issue.
- */
-#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_EXT_INT          FALSE
-#endif
-
 /** @} */
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
index b37c026..e04dff6 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
@@ -117,13 +117,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) {
  * @notapi
  */
 static void nand_ready_isr_enable(NANDDriver *nandp) {
-#if STM32_NAND_USE_EXT_INT
-  nandp->config->ext_nand_isr_enable();
-#else
+
   nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS |
-                                          FSMC_SR_ILEN | FSMC_SR_IFEN);
+                                    FSMC_SR_ILEN | FSMC_SR_IFEN);
   nandp->nand->SR |= FSMC_SR_IREN;
-#endif
 }
 
 /**
@@ -134,11 +131,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) {
  * @notapi
  */
 static void nand_ready_isr_disable(NANDDriver *nandp) {
-#if STM32_NAND_USE_EXT_INT
-  nandp->config->ext_nand_isr_disable();
-#else
+
   nandp->nand->SR &= ~FSMC_SR_IREN;
-#endif
 }
 
 /**
@@ -152,10 +146,8 @@ static void nand_isr_handler (NANDDriver *nandp) {
 
   osalSysLockFromISR();
 
-#if !STM32_NAND_USE_EXT_INT
   osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */
   nandp->nand->SR &= ~FSMC_SR_IRS;
-#endif
 
   switch (nandp->state){
   case NAND_READ:
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
index 5be023e..b0fa72f 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
@@ -120,10 +120,6 @@
 #error "FSMC not present in the selected device"
 #endif
 
-#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT
-#error "External interrupt controller must be enabled to use this feature"
-#endif
-
 #if !defined(STM32_DMA_REQUIRED)
 #define STM32_DMA_REQUIRED
 #endif
@@ -142,13 +138,6 @@ typedef struct NANDDriver NANDDriver;
  */
 typedef void (*nandisrhandler_t)(NANDDriver *nandp);
 
-#if STM32_NAND_USE_EXT_INT
-/**
- * @brief   Type of function switching external interrupts on and off.
- */
-typedef void (*nandisrswitch_t)(void);
-#endif /* STM32_NAND_USE_EXT_INT */
-
 /**
  * @brief   Driver configuration structure.
  * @note    It could be empty on some architectures.
@@ -188,16 +177,6 @@ typedef struct {
    *          from STMicroelectronics.
    */
   uint32_t                  pmem;
-#if STM32_NAND_USE_EXT_INT
-  /**
-   * @brief   Function enabling interrupts from EXTI
-   */
-  nandisrswitch_t           ext_nand_isr_enable;
-  /**
-   * @brief   Function disabling interrupts from EXTI
-   */
-  nandisrswitch_t           ext_nand_isr_disable;
-#endif /* STM32_NAND_USE_EXT_INT */
 } NANDConfig;
 
 /**