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authormarcoveeneman <marco-veeneman@hotmail.com>2014-10-13 23:01:10 +0200
committermarcoveeneman <marco-veeneman@hotmail.com>2014-10-13 23:01:10 +0200
commitb74008c8490fbd6f27392c0badd3de5b6792fc09 (patch)
tree48ae35cc8b12b478edabb854bba972ce87961b98 /os/hal/ports/TIVA/TM4C129x
parented9baddee35122aa2654f3178148fee0d65b9547 (diff)
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Added Tiva HAL files.
Diffstat (limited to 'os/hal/ports/TIVA/TM4C129x')
-rw-r--r--os/hal/ports/TIVA/TM4C129x/hal_lld.c152
-rw-r--r--os/hal/ports/TIVA/TM4C129x/hal_lld.h381
-rw-r--r--os/hal/ports/TIVA/TM4C129x/platform.mk11
-rw-r--r--os/hal/ports/TIVA/TM4C129x/tiva_isr.h569
-rw-r--r--os/hal/ports/TIVA/TM4C129x/tiva_registry.h368
-rw-r--r--os/hal/ports/TIVA/TM4C129x/tm4c129x.h1066
6 files changed, 2547 insertions, 0 deletions
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
new file mode 100644
index 0000000..4f2a968
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
@@ -0,0 +1,152 @@
+/*
+ Copyright (C) 2014 Marco Veeneman
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIVA/TM4C129x/hal_lld.c
+ * @brief TM4C129x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void)
+{
+}
+
+/**
+ * @brief TM4C129x clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p mcuconf.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void tiva_clock_init(void)
+{
+ uint32_t moscctl, rsclkcfg;
+
+ /*
+ * 1. Once POR has completed, the PIOSC is acting as the system clock.
+ */
+
+ /*
+ * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.
+ */
+ moscctl = SYSCTL->MOSCCTL;
+ moscctl &= ~MOSCCTL_NOXTAL;
+
+ /*
+ * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
+ * clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status
+ * (RIS), indicating MOSC crystal mode is ready.
+ */
+#if TIVA_MOSC_SINGLE_ENDED
+ SYSCTL->MOSCCTL = moscctl;
+#else
+ moscctl &= ~MOSCCTL_PWRDN;
+ SYSCTL->MOSCCTL = moscctl;
+
+ while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS));
+#endif
+
+ /*
+ * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.
+ */
+ rsclkcfg = SYSCTL->RSCLKCFG;
+
+ rsclkcfg |= TIVA_RSCLKCFG_OSCSRC;
+
+ /*
+ * 5. If the application also requires the MOSC to be the deep-sleep clock source, then program the
+ * DSOSCSRC field in the DSCLKCFG register to 0x3.
+ */
+
+ /*
+ * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
+ * the configure the desired VCO frequency setting.
+ */
+ SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1
+ SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR;
+
+ /*
+ * 7. Write the MEMTIM0 register to correspond to the new system clock setting.
+ */
+ SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1);
+
+ /*
+ * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
+ * (or that a timeout period has passed and lock has failed, in which case an error condition exists
+ * and this sequence is abandoned and error processing is initiated).
+ */
+ while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK);
+
+ /*
+ * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
+ * bit.
+ */
+
+ rsclkcfg = SYSCTL->RSCLKCFG;
+
+ rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24));
+
+ //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20));
+
+ rsclkcfg |= RSCLKCFG_MEMTIMU;
+
+ // set new configuration
+ SYSCTL->RSCLKCFG = rsclkcfg;
+
+#if HAL_USE_PWM
+#if TIVA_PWM_USE_PWM0
+ PWM0->CC = TIVA_PWM_FIELDS;
+#endif
+#endif
+}
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
new file mode 100644
index 0000000..a0e769b
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
@@ -0,0 +1,381 @@
+/*
+ Copyright (C) 2014 Marco Veeneman
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TIVA/TM4C129x/hal_lld.h
+ * @brief TM4C129x HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - TODO: add required macros
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "tiva_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+
+#define PLATFORM_NAME "Tiva C Series TM4C129x"
+
+/**
+ * @}
+ */
+
+/**
+ * @name RIS register bits definitions
+ * @{
+ */
+
+#define SYSCTL_RIS_PLLLRIS (1 << 6)
+#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)
+
+/**
+ * @}
+ */
+
+/**
+ * @name MOSCCTL register bits definitions
+ * @{
+ */
+
+#define MOSCCTL_CVAL (1 << 0)
+#define MOSCCTL_MOSCIM (1 << 1)
+#define MOSCCTL_NOXTAL (1 << 2)
+#define MOSCCTL_PWRDN (1 << 3)
+#define MOSCCTL_OSCRNG (1 << 4)
+
+/**
+ * @}
+ */
+
+/**
+ * @name RSCLKCFG register bits definitions
+ * @{
+ */
+
+#define RSCLKCFG_PSYSDIV_bm (0xfffff << 0)
+#define RSCLKCFG_OSYSDIV_bm (0xfffff << 10
+
+#define RSCLKCFG_OSCSRC_bm (0xff << 20)
+#define RSCLKCFG_OSCSRC_PIOSC (0 << 20)
+#define RSCLKCFG_OSCSRC_LFIOSC (0x02 << 20)
+#define RSCLKCFG_OSCSRC_MOSC (0x03 << 20)
+#define RSCLKCFG_OSCSRC_RTCOSC (0x04 << 20)
+
+#define RSCLKCFG_PLLSRC_bm (0xff << 24)
+#define RSCLKCFG_PLLSRC_PIOSC (0 << 24)
+#define RSCLKCFG_PLLSRC_MOSC (0x03 << 24)
+
+#define RSCLKCFG_USEPLL (1 << 28)
+
+#define RSCLKCFG_ACG (1 << 29)
+
+#define RSCLKCFG_NEWFREQ (1 << 30)
+
+#define RSCLKCFG_MEMTIMU (1 << 31)
+
+/**
+ * @}
+ */
+
+/**
+ * @name PLLFREQ0 register bits definitions
+ * The PLL frequency can be calculated using the following equation:
+ * fVCO = (fIN * MDIV)
+ * where
+ * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1)
+ * MDIV = MINT + (MFRAC / 1024)
+ * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
+ * should be programmed to 0x0.
+ * @{
+ */
+
+#define PLLFREQ0_MINT_bm (0xfffff << 0)
+#define PLLFREQ0_MFRAC_bm (0xfffff << 10)
+#define PLLFREQ0_PLLPWR (1 << 23)
+
+/**
+ * @}
+ */
+
+/**
+ * @name PLLFREQ1 register bits definitions
+ * @{
+ */
+
+#define PLLFREQ1_N_bm (0x7ff << 0)
+#define PLLFREQ1_Q_bm (0x7ff << 8)
+
+/**
+ * @}
+ */
+
+/**
+ * @name MEMTIM0 register bits definitions
+ * @{
+ */
+
+#define MEMTIM0_FWS_bm (0xff << 0)
+#define MEMTIM0_FWS_0 (0x00 << 0)
+#define MEMTIM0_FWS_1 (0x01 << 0)
+#define MEMTIM0_FWS_2 (0x02 << 0)
+#define MEMTIM0_FWS_3 (0x03 << 0)
+#define MEMTIM0_FWS_4 (0x04 << 0)
+#define MEMTIM0_FWS_5 (0x05 << 0)
+#define MEMTIM0_FWS_6 (0x06 << 0)
+#define MEMTIM0_FWS_7 (0x07 << 0)
+
+#define MEMTIM0_FBCE (1 << 5)
+
+#define MEMTIM0_FBCHT_bm (0xff << 6)
+#define MEMTIM0_FBCHT_0_5 (0x00 << 6)
+#define MEMTIM0_FBCHT_1 (0x01 << 6)
+#define MEMTIM0_FBCHT_1_5 (0x02 << 6)
+#define MEMTIM0_FBCHT_2 (0x03 << 6)
+#define MEMTIM0_FBCHT_2_5 (0x04 << 6)
+#define MEMTIM0_FBCHT_3 (0x05 << 6)
+#define MEMTIM0_FBCHT_3_5 (0x06 << 6)
+#define MEMTIM0_FBCHT_4 (0x07 << 6)
+#define MEMTIM0_FBCHT_4_5 (0x08 << 6)
+
+#define MEMTIM0_EWS_bm (0xff << 16)
+#define MEMTIM0_EWS_0 (0x00 << 16)
+#define MEMTIM0_EWS_1 (0x01 << 16)
+#define MEMTIM0_EWS_2 (0x02 << 16)
+#define MEMTIM0_EWS_3 (0x03 << 16)
+#define MEMTIM0_EWS_4 (0x04 << 16)
+#define MEMTIM0_EWS_5 (0x05 << 16)
+#define MEMTIM0_EWS_6 (0x06 << 16)
+#define MEMTIM0_EWS_7 (0x07 << 16)
+
+#define MEMTIM0_EBCE (1 << 21)
+
+#define MEMTIM0_EBCHT_bm (0xff << 22)
+#define MEMTIM0_EBCHT_0_5 (0x00 << 22)
+#define MEMTIM0_EBCHT_1 (0x01 << 22)
+#define MEMTIM0_EBCHT_1_5 (0x02 << 22)
+#define MEMTIM0_EBCHT_2 (0x03 << 22)
+#define MEMTIM0_EBCHT_2_5 (0x04 << 22)
+#define MEMTIM0_EBCHT_3 (0x05 << 22)
+#define MEMTIM0_EBCHT_3_5 (0x06 << 22)
+#define MEMTIM0_EBCHT_4 (0x07 << 22)
+#define MEMTIM0_EBCHT_4_5 (0x08 << 22)
+
+// XXX: what is this?
+#define MEMTIM0_MB1 0x00100010 // MB1 = Must be one
+
+/**
+ * @}
+ */
+
+/**
+ * @name PLLSTAT register bits definitions
+ * @{
+ */
+
+#define PLLSTAT_LOCK (1 << 0)
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(TIVA_MOSC_SINGLE_ENDED)
+#define TIVA_MOSC_SINGLE_ENDED FALSE
+#endif
+
+#if !defined(TIVA_RSCLKCFG_OSCSRC)
+#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(TM4C129x_MCUCONF)
+#error "Using a wrong mcuconf.h file, TM4C129x_MCUCONF not defined"
+#endif
+
+/*
+ * Oscillator-related checks.
+ */
+#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) && \
+ !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) && \
+ !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) && \
+ !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC)
+#error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined"
+#endif
+
+#if TIVA_XTAL_VALUE == 4000000
+#define TIVA_XTAL_ (0x06 << 6)
+#elif TIVA_XTAL_VALUE == 4096000
+#define TIVA_XTAL_ (0x07 << 6)
+#elif TIVA_XTAL_VALUE == 4915200
+#define TIVA_XTAL_ (0x08 << 6)
+#elif TIVA_XTAL_VALUE == 5000000
+#define TIVA_XTAL_ (0x09 << 6)
+#elif TIVA_XTAL_VALUE == 5120000
+#define TIVA_XTAL_ (0x0a << 6)
+#elif TIVA_XTAL_VALUE == 6000000
+#define TIVA_XTAL_ (0x0b << 6)
+#elif TIVA_XTAL_VALUE == 6144000
+#define TIVA_XTAL_ (0x0c << 6)
+#elif TIVA_XTAL_VALUE == 7372800
+#define TIVA_XTAL_ (0x0d << 6)
+#elif TIVA_XTAL_VALUE == 8000000
+#define TIVA_XTAL_ (0x0e << 6)
+#elif TIVA_XTAL_VALUE == 8192000
+#define TIVA_XTAL_ (0x0f << 6)
+#elif TIVA_XTAL_VALUE == 10000000
+#define TIVA_XTAL_ (0x10 << 6)
+#elif TIVA_XTAL_VALUE == 12000000
+#define TIVA_XTAL_ (0x11 << 6)
+#elif TIVA_XTAL_VALUE == 12288000
+#define TIVA_XTAL_ (0x12 << 6)
+#elif TIVA_XTAL_VALUE == 13560000
+#define TIVA_XTAL_ (0x13 << 6)
+#elif TIVA_XTAL_VALUE == 14318180
+#define TIVA_XTAL_ (0x14 << 6)
+#elif TIVA_XTAL_VALUE == 16000000
+#define TIVA_XTAL_ (0x15 << 6)
+#elif TIVA_XTAL_VALUE == 16384000
+#define TIVA_XTAL_ (0x16 << 6)
+#elif TIVA_XTAL_VALUE == 18000000
+#define TIVA_XTAL_ (0x17 << 6)
+#elif TIVA_XTAL_VALUE == 20000000
+#define TIVA_XTAL_ (0x18 << 6)
+#elif TIVA_XTAL_VALUE == 24000000
+#define TIVA_XTAL_ (0x19 << 6)
+#elif TIVA_XTAL_VALUE == 25000000
+#define TIVA_XTAL_ (0x1a << 6)
+#else
+#error "Invalid value for TIVA_XTAL_VALUE defined"
+#endif
+
+/*
+#if TIVA_MOSC_ENABLE == TRUE
+#define TIVA_MOSCDIS (0 << 0)
+#define TIVA_XTAL TIVA_XTAL_
+#elif TIVA_MOSC_ENABLE == FALSE
+#define TIVA_MOSCDIS (1 << 0)
+#define TIVA_XTAL 0
+#else
+#error "Invalid value for TIVA_MOSC_ENABLE defined"
+#endif
+
+#if TIVA_DIV400_ENABLE == TRUE
+#define TIVA_DIV400 (1 << 30)
+#elif TIVA_DIV400_ENABLE == FALSE
+#define TIVA_DIV400 (0 << 30)
+#else
+#error "Invalid value for TIVA_DIV400_ENABLE defined"
+#endif
+
+#if (TIVA_SYSDIV_VALUE >= 0x02) && (TIVA_SYSDIV_VALUE <= 0x3f)
+#define TIVA_SYSDIV (TIVA_SYSDIV_VALUE << 23)
+#define TIVA_SYSDIV2 (TIVA_SYSDIV_VALUE << 23)
+#else
+#error "Invalid value for TIVA_SYSDIV_VALUE defined"
+#endif
+
+#if TIVA_USESYSDIV_ENABLE == TRUE
+#define TIVA_USESYSDIV (1 << 22)
+#elif TIVA_USESYSDIV_ENABLE == FALSE
+#define TIVA_USESYSDIV (0 << 22)
+#else
+#error "Invalid value for TIVA_USESYSDIV_ENABLE defined"
+#endif
+
+#if TIVA_SYSDIV2LSB_ENABLE == TRUE
+#define TIVA_SYSDIV2LSB (1 << 22)
+#elif TIVA_SYSDIV2LSB_ENABLE == FALSE
+#define TIVA_SYSDIV2LSB (0 << 22)
+#else
+#error "Invalid value for TIVA_SYSDIV2LSB_ENABLE defined"
+#endif
+
+#if TIVA_BYPASS_ENABLE == TRUE
+#define TIVA_SRC 16000000
+#define TIVA_BYPASS (1 << 11)
+#elif TIVA_BYPASS_ENABLE == FALSE
+#define TIVA_SRC (200000000 + ((TIVA_DIV400 >> 30) * 200000000))
+#define TIVA_BYPASS (0 << 11)
+#else
+#error "Invalid value for TIVA_BYPASS_ENABLE defined"
+#endif
+
+#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE)
+#error "Main Oscillator selected but not enabled"
+#endif
+*/
+/*
+ * System Clock calculation
+ * TODO: dynamic TIVA_SYSCLK value
+ */
+#define TIVA_SYSCLK 120000000
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SysTick"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "tiva_isr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void tiva_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
new file mode 100644
index 0000000..83331e0
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -0,0 +1,11 @@
+# List of all the TM4C129x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x \
+ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
new file mode 100644
index 0000000..b995c4f
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
@@ -0,0 +1,569 @@
+/*
+ Copyright (C) 2014 Marco Veeneman
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TM4C129x/tiva_isr.h
+ * @brief TM4C129x ISR remapper driver header.
+ *
+ * @addtogroup TM4C129x_ISR
+ * @{
+ */
+
+#ifndef _TIVA_ISR_H_
+#define _TIVA_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISR names and numbers remapping
+ * @{
+ */
+
+/* GPIO units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
+ || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#define TIVA_GPIOA_HANDLER Vector40
+#define TIVA_GPIOB_HANDLER Vector44
+#define TIVA_GPIOC_HANDLER Vector48
+#define TIVA_GPIOD_HANDLER Vector4C
+#define TIVA_GPIOE_HANDLER Vector50
+#define TIVA_GPIOF_HANDLER VectorB8
+#define TIVA_GPIOG_HANDLER VectorBC
+#define TIVA_GPIOH_HANDLER VectorC0
+#define TIVA_GPIOJ_HANDLER Vector10C
+#define TIVA_GPIOK_HANDLER Vector110
+#define TIVA_GPIOL_HANDLER Vector114
+#define TIVA_GPIOM_HANDLER Vector160
+#define TIVA_GPION_HANDLER Vector164
+#define TIVA_GPIOP0_HANDLER Vector170
+#define TIVA_GPIOP1_HANDLER Vector174
+#define TIVA_GPIOP2_HANDLER Vector178
+#define TIVA_GPIOP3_HANDLER Vector17C
+#define TIVA_GPIOP4_HANDLER Vector180
+#define TIVA_GPIOP5_HANDLER Vector184
+#define TIVA_GPIOP6_HANDLER Vector188
+#define TIVA_GPIOP7_HANDLER Vector18C
+#define TIVA_GPIOQ0_HANDLER Vector190
+#define TIVA_GPIOQ1_HANDLER Vector194
+#define TIVA_GPIOQ2_HANDLER Vector198
+#define TIVA_GPIOQ3_HANDLER Vector19C
+#define TIVA_GPIOQ4_HANDLER Vector1A0
+#define TIVA_GPIOQ5_HANDLER Vector1A4
+#define TIVA_GPIOQ6_HANDLER Vector1A8
+#define TIVA_GPIOQ7_HANDLER Vector1AC
+
+#define TIVA_GPIOA_NUMBER 0
+#define TIVA_GPIOB_NUMBER 1
+#define TIVA_GPIOC_NUMBER 2
+#define TIVA_GPIOD_NUMBER 3
+#define TIVA_GPIOE_NUMBER 4
+#define TIVA_GPIOF_NUMBER 30
+#define TIVA_GPIOG_NUMBER 31
+#define TIVA_GPIOH_NUMBER 32
+#define TIVA_GPIOJ_NUMBER 51
+#define TIVA_GPIOK_NUMBER 52
+#define TIVA_GPIOL_NUMBER 53
+#define TIVA_GPIOM_NUMBER 72
+#define TIVA_GPION_NUMBER 73
+#define TIVA_GPIOP0_NUMBER 76
+#define TIVA_GPIOP1_NUMBER 77
+#define TIVA_GPIOP2_NUMBER 78
+#define TIVA_GPIOP3_NUMBER 79
+#define TIVA_GPIOP4_NUMBER 80
+#define TIVA_GPIOP5_NUMBER 81
+#define TIVA_GPIOP6_NUMBER 82
+#define TIVA_GPIOP7_NUMBER 83
+#define TIVA_GPIOQ0_NUMBER 84
+#define TIVA_GPIOQ1_NUMBER 85
+#define TIVA_GPIOQ2_NUMBER 86
+#define TIVA_GPIOQ3_NUMBER 87
+#define TIVA_GPIOQ4_NUMBER 88
+#define TIVA_GPIOQ5_NUMBER 89
+#define TIVA_GPIOQ6_NUMBER 90
+#define TIVA_GPIOQ7_NUMBER 91
+#endif
+#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
+ || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_GPIOA_HANDLER Vector40
+#define TIVA_GPIOB_HANDLER Vector44
+#define TIVA_GPIOC_HANDLER Vector48
+#define TIVA_GPIOD_HANDLER Vector4C
+#define TIVA_GPIOE_HANDLER Vector50
+#define TIVA_GPIOF_HANDLER VectorB8
+#define TIVA_GPIOG_HANDLER VectorBC
+#define TIVA_GPIOH_HANDLER VectorC0
+#define TIVA_GPIOJ_HANDLER Vector10C
+#define TIVA_GPIOK_HANDLER Vector110
+#define TIVA_GPIOL_HANDLER Vector114
+#define TIVA_GPIOM_HANDLER Vector160
+#define TIVA_GPION_HANDLER Vector164
+#define TIVA_GPIOP0_HANDLER Vector170
+#define TIVA_GPIOP1_HANDLER Vector174
+#define TIVA_GPIOP2_HANDLER Vector178
+#define TIVA_GPIOP3_HANDLER Vector17C
+#define TIVA_GPIOP4_HANDLER Vector180
+#define TIVA_GPIOP5_HANDLER Vector184
+#define TIVA_GPIOP6_HANDLER Vector188
+#define TIVA_GPIOP7_HANDLER Vector18C
+#define TIVA_GPIOQ0_HANDLER Vector190
+#define TIVA_GPIOQ1_HANDLER Vector194
+#define TIVA_GPIOQ2_HANDLER Vector198
+#define TIVA_GPIOQ3_HANDLER Vector19C
+#define TIVA_GPIOQ4_HANDLER Vector1A0
+#define TIVA_GPIOQ5_HANDLER Vector1A4
+#define TIVA_GPIOQ6_HANDLER Vector1A8
+#define TIVA_GPIOQ7_HANDLER Vector1AC
+#define TIVA_GPIOR_HANDLER Vector1B0
+#define TIVA_GPIOS_HANDLER Vector1B4
+#define TIVA_GPIOT_HANDLER Vector1FC
+
+#define TIVA_GPIOA_NUMBER 0
+#define TIVA_GPIOB_NUMBER 1
+#define TIVA_GPIOC_NUMBER 2
+#define TIVA_GPIOD_NUMBER 3
+#define TIVA_GPIOE_NUMBER 4
+#define TIVA_GPIOF_NUMBER 30
+#define TIVA_GPIOG_NUMBER 31
+#define TIVA_GPIOH_NUMBER 32
+#define TIVA_GPIOJ_NUMBER 51
+#define TIVA_GPIOK_NUMBER 52
+#define TIVA_GPIOL_NUMBER 53
+#define TIVA_GPIOM_NUMBER 72
+#define TIVA_GPION_NUMBER 73
+#define TIVA_GPIOP0_NUMBER 76
+#define TIVA_GPIOP1_NUMBER 77
+#define TIVA_GPIOP2_NUMBER 78
+#define TIVA_GPIOP3_NUMBER 79
+#define TIVA_GPIOP4_NUMBER 80
+#define TIVA_GPIOP5_NUMBER 81
+#define TIVA_GPIOP6_NUMBER 82
+#define TIVA_GPIOP7_NUMBER 83
+#define TIVA_GPIOQ0_NUMBER 84
+#define TIVA_GPIOQ1_NUMBER 85
+#define TIVA_GPIOQ2_NUMBER 86
+#define TIVA_GPIOQ3_NUMBER 87
+#define TIVA_GPIOQ4_NUMBER 88
+#define TIVA_GPIOQ5_NUMBER 89
+#define TIVA_GPIOQ6_NUMBER 90
+#define TIVA_GPIOQ7_NUMBER 91
+#define TIVA_GPIOR_NUMBER 92
+#define TIVA_GPIOS_NUMBER 93
+#define TIVA_GPIOT_NUMBER 111
+#endif
+
+/* EPI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_EPI0_HANDLER Vector108
+
+#define TIVA_EPI0_NUMBER 50
+#endif
+
+/* CRC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+/* CRC has no interrupts.*/
+#endif
+
+/* AES Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_AES_HANDLER Vector1BC
+
+#define TIVA_AES_NUMBER 95
+#endif
+
+/* DES Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_DES_HANDLER Vector1C0
+
+#define TIVA_DES_NUMBER 51
+#endif
+
+/* SHA/MD5 Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_SHA_MD5_HANDLER Vector1B8
+
+#define TIVA_SHA_MD5_NUMBER 94
+#endif
+
+/* GPT units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_GPT0A_HANDLER Vector8C
+#define TIVA_GPT0B_HANDLER Vector90
+#define TIVA_GPT1A_HANDLER Vector94
+#define TIVA_GPT1B_HANDLER Vector98
+#define TIVA_GPT2A_HANDLER Vector9C
+#define TIVA_GPT2B_HANDLER VectorA0
+#define TIVA_GPT3A_HANDLER VectorCC
+#define TIVA_GPT3B_HANDLER VectorD0
+#define TIVA_GPT4A_HANDLER Vector13C
+#define TIVA_GPT4B_HANDLER Vector140
+#define TIVA_GPT5A_HANDLER Vector144
+#define TIVA_GPT5B_HANDLER Vector148
+#define TIVA_GPT6A_HANDLER Vector1C8
+#define TIVA_GPT6B_HANDLER Vector1CC
+#define TIVA_GPT7A_HANDLER Vector1D0
+#define TIVA_GPT7B_HANDLER Vector1D4
+
+#define TIVA_GPT0A_NUMBER 19
+#define TIVA_GPT0B_NUMBER 20
+#define TIVA_GPT1A_NUMBER 21
+#define TIVA_GPT1B_NUMBER 22
+#define TIVA_GPT2A_NUMBER 23
+#define TIVA_GPT2B_NUMBER 24
+#define TIVA_GPT3A_NUMBER 35
+#define TIVA_GPT3B_NUMBER 36
+#define TIVA_GPT4A_NUMBER 63
+#define TIVA_GPT4B_NUMBER 64
+#define TIVA_GPT5A_NUMBER 65
+#define TIVA_GPT5B_NUMBER 66
+#define TIVA_GPT6A_NUMBER 98
+#define TIVA_GPT6B_NUMBER 99
+#define TIVA_GPT7A_NUMBER 100
+#define TIVA_GPT7B_NUMBER 101
+#endif
+
+/* WDT units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_WDT_HANDLER Vector88
+
+#define TIVA_WDT_NUMBER 18
+#endif
+
+/* ADC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_ADC0_SEQ0_HANDLER Vector78
+#define TIVA_ADC0_SEQ1_HANDLER Vector7C
+#define TIVA_ADC0_SEQ2_HANDLER Vector80
+#define TIVA_ADC0_SEQ3_HANDLER Vector84
+#define TIVA_ADC1_SEQ0_HANDLER VectorF8
+#define TIVA_ADC1_SEQ1_HANDLER VectorFC
+#define TIVA_ADC1_SEQ2_HANDLER Vector100
+#define TIVA_ADC1_SEQ3_HANDLER Vector104
+
+#define TIVA_ADC0_SEQ0_NUMBER 14
+#define TIVA_ADC0_SEQ1_NUMBER 15
+#define TIVA_ADC0_SEQ2_NUMBER 16
+#define TIVA_ADC0_SEQ3_NUMBER 17
+#define TIVA_ADC1_SEQ0_NUMBER 46
+#define TIVA_ADC1_SEQ1_NUMBER 47
+#define TIVA_ADC1_SEQ2_NUMBER 48
+#define TIVA_ADC1_SEQ3_NUMBER 49
+#endif
+
+/* UART units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_UART0_HANDLER Vector54
+#define TIVA_UART1_HANDLER Vector58
+#define TIVA_UART2_HANDLER VectorC4
+#define TIVA_UART3_HANDLER Vector120
+#define TIVA_UART4_HANDLER Vector124
+#define TIVA_UART5_HANDLER Vector128
+#define TIVA_UART6_HANDLER Vector12C
+#define TIVA_UART7_HANDLER Vector130
+
+#define TIVA_UART0_NUMBER 5
+#define TIVA_UART1_NUMBER 6
+#define TIVA_UART2_NUMBER 33
+#define TIVA_UART3_NUMBER 56
+#define TIVA_UART4_NUMBER 57
+#define TIVA_UART5_NUMBER 58
+#define TIVA_UART6_NUMBER 59
+#define TIVA_UART7_NUMBER 60
+#endif
+
+/* QSSI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_QSSI0_HANDLER Vector5C
+#define TIVA_QSSI1_HANDLER VectorC8
+#define TIVA_QSSI2_HANDLER Vector118
+#define TIVA_QSSI3_HANDLER Vector11C
+
+#define TIVA_QSSI0_NUMBER 7
+#define TIVA_QSSI1_NUMBER 34
+#define TIVA_QSSI2_NUMBER 54
+#define TIVA_QSSI3_NUMBER 55
+#endif
+
+/* I2C units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_I2C0_HANDLER Vector60
+#define TIVA_I2C1_HANDLER VectorD4
+#define TIVA_I2C2_HANDLER Vector134
+#define TIVA_I2C3_HANDLER Vector138
+#define TIVA_I2C4_HANDLER Vector158
+#define TIVA_I2C5_HANDLER Vector15C
+#define TIVA_I2C6_HANDLER Vector1D8
+#define TIVA_I2C7_HANDLER Vector1DC
+#define TIVA_I2C8_HANDLER Vector1F4
+#define TIVA_I2C9_HANDLER Vector1F8
+
+#define TIVA_I2C0_NUMBER 8
+#define TIVA_I2C1_NUMBER 37
+#define TIVA_I2C2_NUMBER 61
+#define TIVA_I2C3_NUMBER 62
+#define TIVA_I2C4_NUMBER 70
+#define TIVA_I2C5_NUMBER 71
+#define TIVA_I2C6_NUMBER 102
+#define TIVA_I2C7_NUMBER 103
+#define TIVA_I2C8_NUMBER 109
+#define TIVA_I2C9_NUMBER 110
+#endif
+
+/* 1-Wire Master units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#define TIVA_HAS_1WIRE FALSE
+#endif
+#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_1WIRE_HANDLER Vector1E4
+
+#define TIVA_1WIRE_NUMBER 105
+#endif
+
+/* CAN units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_CAN0_HANDLER VectorD8
+#define TIVA_CAN1_HANDLER VectorDC
+
+#define TIVA_CAN0_NUMBER 38
+#define TIVA_CAN1_NUMBER 39
+#endif
+
+/* Ethernet MAC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
+ || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
+ || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
+ || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_MAC_HANDLER VectorE0
+
+#define TIVA_MAC_NUMBER 40
+#endif
+
+/* Ethernet PHY units.*/
+#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
+ || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
+ || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+/* no interrupts.*/
+#endif
+
+/* USB units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_USB0_HANDLER VectorE8
+
+#define TIVA_USB0_NUMBER 42
+#endif
+
+/* LCD units.*/
+#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_LCD_HANDLER Vector1C4
+
+#define TIVA_LCD_NUMBER 97
+#endif
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+/* no interrupts.*/
+#endif
+
+/* AC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_AC0_HANDLER VectorA4
+#define TIVA_AC1_HANDLER VectorA8
+#define TIVA_AC2_HANDLER VectorAC
+
+#define TIVA_AC0_NUMBER 25
+#define TIVA_AC1_NUMBER 26
+#define TIVA_AC2_NUMBER 27
+#endif
+
+/* PWM units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_PWM0FAULT_HANDLER Vector64
+#define TIVA_PWM0GEN0_HANDLER Vector68
+#define TIVA_PWM0GEN1_HANDLER Vector6C
+#define TIVA_PWM0GEN2_HANDLER Vector70
+#define TIVA_PWM0GEN3_HANDLER VectorEC
+
+#define TIVA_PWM0FAULT_NUMBER 9
+#define TIVA_PWM0GEN0_NUMBER 10
+#define TIVA_PWM0GEN1_NUMBER 11
+#define TIVA_PWM0GEN2_NUMBER 12
+#define TIVA_PWM0GEN3_NUMBER 43
+#endif
+
+/* QEI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_QEI0_HANLDER Vector74
+
+#define TIVA_QEI0_NUMBER 13
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* _TIVA_ISR_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
new file mode 100644
index 0000000..e38ee51
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -0,0 +1,368 @@
+/*
+ Copyright (C) 2014 Marco Veeneman
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TM4C129x/tiva_registry.h
+ * @brief TM4C123x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _TIVA_REGISTRY_H_
+#define _TIVA_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name TM4C129x capabilities
+ * @{
+ */
+
+/* GPIO attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
+ || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#define TIVA_HAS_GPIOA TRUE
+#define TIVA_HAS_GPIOB TRUE
+#define TIVA_HAS_GPIOC TRUE
+#define TIVA_HAS_GPIOD TRUE
+#define TIVA_HAS_GPIOE TRUE
+#define TIVA_HAS_GPIOF TRUE
+#define TIVA_HAS_GPIOG TRUE
+#define TIVA_HAS_GPIOH TRUE
+#define TIVA_HAS_GPIOJ TRUE
+#define TIVA_HAS_GPIOK TRUE
+#define TIVA_HAS_GPIOL TRUE
+#define TIVA_HAS_GPIOM TRUE
+#define TIVA_HAS_GPION TRUE
+#define TIVA_HAS_GPIOP TRUE
+#define TIVA_HAS_GPIOQ TRUE
+#define TIVA_HAS_GPIOR FALSE
+#define TIVA_HAS_GPIOS FALSE
+#define TIVA_HAS_GPIOT FALSE
+#endif
+#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
+ || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_GPIOA TRUE
+#define TIVA_HAS_GPIOB TRUE
+#define TIVA_HAS_GPIOC TRUE
+#define TIVA_HAS_GPIOD TRUE
+#define TIVA_HAS_GPIOE TRUE
+#define TIVA_HAS_GPIOF TRUE
+#define TIVA_HAS_GPIOG TRUE
+#define TIVA_HAS_GPIOH TRUE
+#define TIVA_HAS_GPIOJ TRUE
+#define TIVA_HAS_GPIOK TRUE
+#define TIVA_HAS_GPIOL TRUE
+#define TIVA_HAS_GPIOM TRUE
+#define TIVA_HAS_GPION TRUE
+#define TIVA_HAS_GPIOP TRUE
+#define TIVA_HAS_GPIOQ TRUE
+#define TIVA_HAS_GPIOR TRUE
+#define TIVA_HAS_GPIOS TRUE
+#define TIVA_HAS_GPIOT TRUE
+#endif
+
+/* EPI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_EPI0 TRUE
+#endif
+
+/* CRC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_CRC0 TRUE
+#endif
+
+/* AES Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+#define TIVA_HAS_AES FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_HAS_AES TRUE
+#endif
+
+/* DES Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+#define TIVA_HAS_DES FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_HAS_DES TRUE
+#endif
+
+/* SHA/MD5 Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD)
+#define TIVA_HAS_SHA_MD5 FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+ || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+ || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+ || defined(TM4C129XNCZAD)
+#define TIVA_HAS_SHA_MD5 TRUE
+#endif
+
+/* GPT attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_GPT0 TRUE
+#define TIVA_HAS_GPT1 TRUE
+#define TIVA_HAS_GPT2 TRUE
+#define TIVA_HAS_GPT3 TRUE
+#define TIVA_HAS_GPT4 TRUE
+#define TIVA_HAS_GPT5 TRUE
+#define TIVA_HAS_GPT6 TRUE
+#define TIVA_HAS_GPT7 TRUE
+#define TIVA_HAS_WGPT0 FALSE
+#define TIVA_HAS_WGPT1 FALSE
+#define TIVA_HAS_WGPT2 FALSE
+#define TIVA_HAS_WGPT3 FALSE
+#define TIVA_HAS_WGPT4 FALSE
+#define TIVA_HAS_WGPT5 FALSE
+#endif
+
+/* WDT attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_WDT0 TRUE
+#define TIVA_HAS_WDT1 TRUE
+#endif
+
+/* ADC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ADC0 TRUE
+#define TIVA_HAS_ADC1 TRUE
+#endif
+
+/* UART attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_UART0 TRUE
+#define TIVA_HAS_UART1 TRUE
+#define TIVA_HAS_UART2 TRUE
+#define TIVA_HAS_UART3 TRUE
+#define TIVA_HAS_UART4 TRUE
+#define TIVA_HAS_UART5 TRUE
+#define TIVA_HAS_UART6 TRUE
+#define TIVA_HAS_UART7 TRUE
+#endif
+
+/* QSSI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_QSSI0 TRUE
+#define TIVA_HAS_QSSI1 TRUE
+#define TIVA_HAS_QSSI2 TRUE
+#define TIVA_HAS_QSSI3 TRUE
+#endif
+
+/* I2C attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_I2C0 TRUE
+#define TIVA_HAS_I2C1 TRUE
+#define TIVA_HAS_I2C2 TRUE
+#define TIVA_HAS_I2C3 TRUE
+#define TIVA_HAS_I2C4 TRUE
+#define TIVA_HAS_I2C5 TRUE
+#define TIVA_HAS_I2C6 TRUE
+#define TIVA_HAS_I2C7 TRUE
+#define TIVA_HAS_I2C8 TRUE
+#define TIVA_HAS_I2C9 TRUE
+#endif
+
+/* 1-Wire Master attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#define TIVA_HAS_1WIRE FALSE
+#endif
+#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_1WIRE TRUE
+#endif
+
+/* CAN attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_CAN0 TRUE
+#define TIVA_HAS_CAN1 TRUE
+#endif
+
+/* Ethernet MAC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
+ || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+#define TIVA_HAS_ETHERNET_MAC FALSE
+#endif
+#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
+ || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
+ || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ETHERNET_MAC TRUE
+#endif
+
+/* Ethernet PHY attributes.*/
+#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
+ || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+#define TIVA_HAS_ETHERNET_PHY FALSE
+#endif
+#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
+ || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ETHERNET_PHY TRUE
+#endif
+
+/* USB attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_USB0 TRUE
+#endif
+
+/* LCD attributes.*/
+#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
+ || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_LCD TRUE
+#endif
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
+ || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+#define TIVA_HAS_LCD FALSE
+#endif
+
+/* AC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_AC0 TRUE
+#define TIVA_HAS_AC1 TRUE
+#define TIVA_HAS_AC2 TRUE
+#endif
+
+/* PWM attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_PWM0 TRUE
+#define TIVA_HAS_PWM1 FALSE
+#endif
+
+/* QEI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+ || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+ || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+ || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+ || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+ || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+ || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_QEI0 TRUE
+#define TIVA_HAS_QEI1 FALSE
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _TIVA_REGISTRY_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
new file mode 100644
index 0000000..1d5c50a
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
@@ -0,0 +1,1066 @@
+/*
+ Copyright (C) 2014 Marco Veeneman
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @addtogroup CMSIS
+ * @{
+ */
+
+/**
+ * @addtogroup TM4C129x
+ * @{
+ */
+
+#ifndef __TM4C129x_H
+#define __TM4C129x_H
+
+/**
+ * @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /**< MPU present */
+#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Use different SysTick Config */
+#define __FPU_PRESENT 1 /**< FPU present */
+
+/**
+ * @brief TM4C129x Interrupt Number Definitions
+ */
+typedef enum IRQn
+{
+ /* TODO: check interrupt numbers with tm4c129 device */
+ /***** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< Cortex-M4 Non-Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -3, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+ /***** TM4C129x Specific Interrupt Numbers *********************************/
+ GPIOA_IRQn = 0, /**< GPIO Port A */
+ GPIOB_IRQn = 1, /**< GPIO Port B */
+ GPIOC_IRQn = 2, /**< GPIO Port C */
+ GPIOD_IRQn = 3, /**< GPIO Port D */
+ GPIOE_IRQn = 4, /**< GPIO Port E */
+ UART0_IRQn = 5, /**< UART0 */
+ UART1_IRQn = 6, /**< UART1 */
+ SSI0_IRQn = 7, /**< SSI0 */
+ I2C0_IRQn = 8, /**< I2C0 */
+ PWM0FAULT_IRQn = 9, /**< PWM0 Fault */
+ PWM0GEN0_IRQn = 10, /**< PWM0 Generator 0 */
+ PWM0GEN1_IRQn = 11, /**< PWM0 Generator 1 */
+ PWM0GEN2_IRQn = 12, /**< PWM0 Generator 2 */
+ QEI0_IRQn = 13, /**< QEI0 */
+ ADC0SEQ0_IRQn = 14, /**< ADC0 Sequence 0 */
+ ADC0SEQ1_IRQn = 15, /**< ADC0 Sequence 1 */
+ ADC0SEQ2_IRQn = 16, /**< ADC0 Sequence 2 */
+ ADC0SEQ3_IRQn = 17, /**< ADC0 Sequence 3 */
+ WATCHDOG_IRQn = 18, /**< Watchdog Timers 0 and 1 */
+ TIMER0A_IRQn = 19, /**< 16/32-Bit Timer 0A */
+ TIMER0B_IRQn = 20, /**< 16/32-Bit Timer 0B */
+ TIMER1A_IRQn = 21, /**< 16/32-Bit Timer 1A */
+ TIMER1B_IRQn = 22, /**< 16/32-Bit Timer 1B */
+ TIMER2A_IRQn = 23, /**< 16/32-Bit Timer 2A */
+ TIMER2B_IRQn = 24, /**< 16/32-Bit Timer 2B */
+ ACOMP0_IRQn = 25, /**< Analog Comparator 0 */
+ ACOMP1_IRQn = 26, /**< Analog Comparator 1 */
+ SYSCON_IRQn = 28, /**< System Control */
+ FMCEECON_IRQn = 29, /**< Flash Memory Control and EEPROM Control */
+ GPIOF_IRQn = 30, /**< GPIO Port F */
+ UART2_IRQn = 33, /**< UART2 */
+ SSI1_IRQn = 34, /**< SSI1 */
+ TIMER3A_IRQn = 35, /**< 16/32-Bit Timer 3A */
+ TIMER3B_IRQn = 36, /**< 16/32-Bit Timer 3B */
+ I2C1_IRQn = 37, /**< I2C1 */
+ QEI1_IRQn = 38, /**< QEI1 */
+ CAN0_IRQn = 39, /**< CAN0 */
+ CAN1_IRQn = 40, /**< CAN1 */
+ HIBMODULE_IRQn = 43, /**< Hibernation Module */
+ USB_IRQn = 44, /**< USB */
+ PWM0GEN3_IRQn = 45, /**< PWM0 Generator 3 */
+ UDMASFW_IRQn = 46, /**< UDMA Software */
+ UDMAERR_IRQn = 47, /**< UDMA Error */
+ ADC1SEQ0_IRQn = 48, /**< ADC1 Sequence 0 */
+ ADC1SEQ1_IRQn = 49, /**< ADC1 Sequence 1 */
+ ADC1SEQ2_IRQn = 50, /**< ADC1 Sequence 2 */
+ ADC1SEQ3_IRQn = 51, /**< ADC1 Sequence 3 */
+ SSI2_IRQn = 57, /**< SSI2 */
+ SSI3_IRQn = 58, /**< SSI3 */
+ UART3_IRQn = 59, /**< UART3 */
+ UART4_IRQn = 60, /**< UART4 */
+ UART5_IRQn = 61, /**< UART5 */
+ UART6_IRQn = 62, /**< UART6 */
+ UART7_IRQn = 63, /**< UART7 */
+ I2C2_IRQn = 68, /**< I2C2 */
+ I2C3_IRQn = 69, /**< I2C3 */
+ TIMER4A_IRQn = 70, /**< 16/32-Bit Timer 4A */
+ TIMER4B_IRQn = 71, /**< 16/32-Bit Timer 4B */
+ TIMER5A_IRQn = 92, /**< 16/32-Bit Timer 5A */
+ TIMER5B_IRQn = 93, /**< 16/32-Bit Timer 5B */
+ WTIMER0A_IRQn = 94, /**< 32/64-Bit Timer 0A */
+ WTIMER0B_IRQn = 95, /**< 32/64-Bit Timer 0B */
+ WTIMER1A_IRQn = 96, /**< 32/64-Bit Timer 1A */
+ WTIMER1B_IRQn = 97, /**< 32/64-Bit Timer 1B */
+ WTIMER2A_IRQn = 98, /**< 32/64-Bit Timer 2A */
+ WTIMER2B_IRQn = 99, /**< 32/64-Bit Timer 2B */
+ WTIMER3A_IRQn = 100, /**< 32/64-Bit Timer 3A */
+ WTIMER3B_IRQn = 101, /**< 32/64-Bit Timer 3B */
+ WTIMER4A_IRQn = 102, /**< 32/64-Bit Timer 4A */
+ WTIMER4B_IRQn = 103, /**< 32/64-Bit Timer 4B */
+ WTIMER5A_IRQn = 104, /**< 32/64-Bit Timer 5A */
+ WTIMER5B_IRQn = 105, /**< 32/64-Bit Timer 5B */
+ SYSEXCEPT_IRQn = 106, /**< System Exception (imprecise) */
+ PWM1GEN0_IRQn = 134, /**< PWM1 Generator 0 */
+ PWM1GEN1_IRQn = 135, /**< PWM1 Generator 1 */
+ PWM1GEN2_IRQn = 136, /**< PWM1 Generator 2 */
+ PWM1GEN3_IRQn = 137, /**< PWM1 Generator 3 */
+ PWM1FAULT_IRQn = 138 /**< PWM1 Fault */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals.*/
+#include <stdint.h>
+
+/**
+ * @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief System Control
+ */
+typedef struct
+{
+ __I uint32_t DID0; /**< Device Identification 0 */
+ __I uint32_t DID1; /**< Device Identification 1 */
+ __I uint32_t RESERVED0[12]; /**< Reserved */
+ __IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */
+ __I uint32_t RESERVED1[5]; /**< Reserved */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t IMC; /**< Interrupt Mask Control */
+ __IO uint32_t MISC; /**< Interrupt Status and Clear */
+ __IO uint32_t RESC; /**< Reset Cause */
+ __IO uint32_t PWRTC; /**< Power-Temperature Cause */
+ __IO uint32_t NMIC; /**< NMI Cause Register */
+ __I uint32_t RESERVED2[5]; /**< Reserved */
+ __IO uint32_t MOSCCTL; /**< Main Oscillator Control */
+ __I uint32_t RESERVED3[12]; /**< Reserved */
+ __IO uint32_t RSCLKCFG; /**< Run and Sleep Mode Configuration Register */
+ __I uint32_t RESERVEDx[3];
+ __IO uint32_t MEMTIM0; /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
+ __I uint32_t RESERVED4[29]; /**< Reserved */
+ __IO uint32_t ALTCLKCFG; /**< Alternate Clock Configuration */
+ __I uint32_t RESERVED5[2]; /**< Reserved */
+ __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */
+ __IO uint32_t DIVSCLK; /**< Divisor and Source Clock Configuration */
+ __I uint32_t SYSPROP; /**< System Properties */
+ __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */
+ __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */
+ __I uint32_t RESERVED6[2]; /**< Reserved */
+ __IO uint32_t PLLFREQ0; /**< PLL Frequency 0 */
+ __IO uint32_t PLLFREQ1; /**< PLL Frequency 1 */
+ __I uint32_t PLLSTAT; /**< PLL Frequency Status */
+ __I uint32_t RESERVED7[7]; /**< Reserved */
+ __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */
+ __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */
+ __I uint32_t RESERVED8[4]; /**< Reserved */
+ __I uint32_t NVMSTAT; /**< Non-Volatile Memory Information */
+ __I uint32_t RESERVED9[4]; /**< Reserved */
+ __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */
+ __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */
+ __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */
+ __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */
+ __I uint32_t RESERVED10[2]; /**< Reserved */
+ __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */
+ __I uint32_t RESERVED11[2]; /**< Reserved */
+ __IO uint32_t RESBEHAVCTL; /**< Reset Behavior Control Register */
+ __I uint32_t RESERVED12[6]; /**< Reserved */
+ __IO uint32_t HSSR; /**< Hardware System Service Request */
+ __I uint32_t RESERVED[34]; /**< Reserved */
+ __I uint32_t USBPDS; /**< USB Power Domain Status */
+ __IO uint32_t USBMPC; /**< USB Memory Power Control */
+ __I uint32_t EMACPDS; /**< Ethernet MAC Power Domain Status */
+ __IO uint32_t EMACMPC; /**< Ethernet MAC Memory Power Control */
+ __I uint32_t RESERVED13[2]; /**< Reserved */
+ __I uint32_t CAN0PDS; /**< CAN 0 Power Domain Status */
+ __IO uint32_t CAN0MPC; /**< CAN 0 Memory Power Control */
+ __I uint32_t CAN1PDS; /**< CAN 1 Power Domain Status */
+ __IO uint32_t CAN1MPC; /**< CAN 1 Memory Power Control */
+ __I uint32_t RESERVED14[22]; /**< Reserved */
+ __I uint32_t PPWD; /**< WDT Peripheral Present */
+ __I uint32_t PPTIMER; /**< GPT Peripheral Present */
+ __I uint32_t PPGPIO; /**< GPIO Peripheral Present */
+ __I uint32_t PPDMA; /**< UDMA Peripheral Present */
+ __I uint32_t PPEPI; /**< EPI Peripheral Present */
+ __I uint32_t PPHIB; /**< HIB Peripheral Present */
+ __I uint32_t PPUART; /**< UART Peripheral Present */
+ __I uint32_t PPSSI; /**< SSI Peripheral Present */
+ __I uint32_t PPI2C; /**< I2C Peripheral Present */
+ __I uint32_t RESERVED15[1]; /**< Reserved */
+ __I uint32_t PPUSB; /**< USB Peripheral Present */
+ __I uint32_t RESERVED16[1]; /**< Reserved */
+ __I uint32_t PPEPHY; /**< Ethernet PHY Peripheral Present */
+ __I uint32_t PPCAN; /**< CAN Peripheral Present */
+ __I uint32_t PPADC; /**< ADC Peripheral Present */
+ __I uint32_t PPACMP; /**< ACMP Peripheral Present */
+ __I uint32_t PPPWM; /**< PWM Peripheral Present */
+ __I uint32_t PPQEI; /**< QEI Peripheral Present */
+ __I uint32_t PPLPC; /**< Low Pin Count Interface Peripheral Present */
+ __I uint32_t RESERVED17[1]; /**< Reserved */
+ __I uint32_t PPPECI; /**< Platform Environment Control Interface Peripheral Present */
+ __I uint32_t PPFAN; /**< Fan Control Peripheral Present */
+ __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */
+ __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */
+ __I uint32_t RESERVED18[4]; /**< Reserved */
+ __I uint32_t PPRTS; /**< Remote Temperature Sensor Peripheral Present */
+ __I uint32_t PPCCM; /**< CRC Module Peripheral Present */
+ __I uint32_t RESERVED19[6]; /**< Reserved */
+ __I uint32_t PPLCD; /**< LCD Peripheral Present */
+ __I uint32_t RESERVED20[1]; /**< Reserved */
+ __I uint32_t PPOWIRE; /**< 1-Wire Peripheral Present */
+ __I uint32_t PPEMAC; /**< Ethernet MAC Peripheral Present */
+ __I uint32_t PPPRB; /**< Power Regulator Bus Peripheral Present */
+ __I uint32_t PPHIM; /**< Human Interface Master Peripheral Present */
+ __I uint32_t RESERVED21[86]; /**< Reserved */
+ __IO uint32_t SRWD; /**< WDT Software Reset */
+ __IO uint32_t SRTIMER; /**< GPT Software Reset */
+ __IO uint32_t SRGPIO; /**< GPIO Software Reset */
+ __IO uint32_t SRDMA; /**< UDMA Software Reset */
+ __IO uint32_t SREPI; /**< EPI Software Reset */
+ __IO uint32_t SRHIB; /**< HIB Software Reset */
+ __IO uint32_t SRUART; /**< UART Software Reset */
+ __IO uint32_t SRSSI; /**< SSI Software Reset */
+ __IO uint32_t SRI2C; /**< I2C Software Reset */
+ __I uint32_t RESERVED22[1]; /**< Reserved */
+ __IO uint32_t SRUSB; /**< USB Software Reset */
+ __I uint32_t RESERVED23[1]; /**< Reserved */
+ __IO uint32_t SREPHY; /**< Ethernet PHY Software Reset */
+ __IO uint32_t SRCAN; /**< CAN Software Reset */
+ __IO uint32_t SRADC; /**< ADC Software Reset */
+ __IO uint32_t SRACMP; /**< ACMP Software Reset */
+ __IO uint32_t SRPWM; /**< PWM Software Reset */
+ __IO uint32_t SRQEI; /**< QEI Software Reset */
+ __I uint32_t RESERVED24[4]; /**< Reserved */
+ __IO uint32_t SREEPROM; /**< EEPROM Software Reset */
+ __I uint32_t RESERVED25[6]; /**< Reserved */
+ __IO uint32_t SRCCM; /**< CRC Module Software Reset */
+ __I uint32_t RESERVED26[9]; /**< Reserved */
+ __IO uint32_t SREMAC; /**< Ethernet MAC Software Reset */
+ __I uint32_t RESERVED27[24]; /**< Reserved */
+ __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */
+ __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */
+ __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */
+ __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */
+ __IO uint32_t RCGCEPI; /**< EPI Run Mode Clock Gating Control */
+ __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */
+ __IO uint32_t RCGCUART; /**< UART Run Mode Control */
+ __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */
+ __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */
+ __I uint32_t RESERVED28[1]; /**< Reserved */
+ __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */
+ __I uint32_t RESERVED29[1]; /**< Reserved */
+ __IO uint32_t RCGCEPHY; /**< Ethernet PHY Run Mode Clock Gating Control */
+ __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */
+ __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */
+ __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */
+ __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */
+ __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */
+ __I uint32_t RESERVED30[4]; /**< Reserved */
+ __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */
+ __I uint32_t RESERVED31[6]; /**< Reserved */
+ __IO uint32_t RCGCCCM; /**< CRC Module Run Mode Clock Gating Control */
+ __I uint32_t RESERVED32[9]; /**< Reserved */
+ __IO uint32_t RCGCEMAC; /**< Ethernet MAC Run Mode Clock Gating Control */
+ __I uint32_t RESERVED33[24]; /**< Reserved */
+ __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCEPI; /**< EPI Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED34[1]; /**< Reserved */
+ __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED35[1]; /**< Reserved */
+ __IO uint32_t SCGCEPHY; /**< Ethernet PHY Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED36[4]; /**< Reserved */
+ __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED37[6]; /**< Reserved */
+ __IO uint32_t SCGCCCM; /**< CRC Module Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED38[9]; /**< Reserved */
+ __IO uint32_t SCGCEMAC; /**< Ethernet MAC Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED39[24]; /**< Reserved */
+ __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCEPI; /**< EPI Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED40[1]; /**< Reserved */
+ __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED41[1]; /**< Reserved */
+ __IO uint32_t DCGCEPHY; /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED42[4]; /**< Reserved */
+ __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating
+ Control */
+ __I uint32_t RESERVED43[6]; /**< Reserved */
+ __IO uint32_t DCGCCCM; /**< CRC Module Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED44[9]; /**< Reserved */
+ __IO uint32_t DCGCEMAC; /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED45[24]; /**< Reserved */
+ __IO uint32_t PCWD; /**< Watchdog Timer Power Control */
+ __IO uint32_t PCTIMER; /**< 16/32-Bit General-Purpose Timer Power Control */
+ __IO uint32_t PCGPIO; /**< General-Purpose Input/Output Power Control */
+ __IO uint32_t PCDMA; /**< Micro Direct Memory Access Power Control */
+ __IO uint32_t PCEPI; /**< External Peripheral Interface Power Control */
+ __IO uint32_t PCHIB; /**< Hibernation Power Control */
+ __IO uint32_t PCUART; /**< Universal Asynchronous Receiver/Transmitter Power Control */
+ __IO uint32_t PCSSI; /**< Synchronous Serial Interface Power Control */
+ __IO uint32_t PCI2C; /**< Inter-Integrated Circuit Power Control */
+ __I uint32_t RESERVED46[1]; /**< Reserved */
+ __IO uint32_t PCUSB; /**< Universal Serial Bus Power Control */
+ __I uint32_t RESERVED47[1]; /**< Reserved */
+ __IO uint32_t PCEPHY; /**< Ethernet PHY Power Control */
+ __IO uint32_t PCCAN; /**< Controller Area Network Power Control */
+ __IO uint32_t PCADC; /**< Analog-to-Digital Converter Power Control */
+ __IO uint32_t PCACMP; /**< Analog Comparator Power Control */
+ __IO uint32_t PCPWM; /**< Pulse Width Modulator Power Control */
+ __IO uint32_t PCQEI; /**< Quadrature Encoder Interface Power Control */
+ __I uint32_t RESERVED48[4]; /**< Reserved */
+ __IO uint32_t PCEEPROM; /**< EEPROM Power Control */
+ __I uint32_t RESERVED49[6]; /**< Reserved */
+ __IO uint32_t PCCCM; /**< CRC Module Power Control */
+ __I uint32_t RESERVED50[9]; /**< Reserved */
+ __IO uint32_t PCEMAC; /**< Ethernet MAC Power Control */
+ __I uint32_t RESERVED51[24]; /**< Reserved */
+ __IO uint32_t PRWD; /**< WDT Peripheral Ready */
+ __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */
+ __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */
+ __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */
+ __IO uint32_t PREPI; /**< EPI Peripheral Ready */
+ __IO uint32_t PRHIB; /**< HIB Peripheral Ready */
+ __IO uint32_t PRUART; /**< UART Peripheral Ready */
+ __IO uint32_t PRSSI; /**< SSI Peripheral Ready */
+ __IO uint32_t PRI2C; /**< I2C Peripheral Ready */
+ __I uint32_t RESERVED52[1]; /**< Reserved */
+ __IO uint32_t PRUSB; /**< USB Peripheral Ready */
+ __I uint32_t RESERVED53[1]; /**< Reserved */
+ __IO uint32_t PREPHY; /**< Ethernet PHY Peripheral Ready */
+ __IO uint32_t PRCAN; /**< CAN Peripheral Ready */
+ __IO uint32_t PRADC; /**< ADC Peripheral Ready */
+ __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */
+ __IO uint32_t PRPWM; /**< PWM Peripheral Ready */
+ __IO uint32_t PRQEI; /**< QEI Peripheral Ready */
+ __I uint32_t RESERVED54[4]; /**< Reserved */
+ __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */
+ __I uint32_t RESERVED55[6]; /**< Reserved */
+ __IO uint32_t PRCCM; /**< CRC Module Peripheral Ready */
+ __I uint32_t RESERVED56[9]; /**< Reserved */
+ __IO uint32_t PREMAC; /**< Ethernet MAC Peripheral Ready */
+} SYSCTL_TypeDef;
+
+/**
+ * @brief Hibernation Module
+ */
+typedef struct
+{
+ __I uint32_t RTCC; /**< RTC Counter */
+ __IO uint32_t RTCM0; /**< RTC Match 0 */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t RTCLD; /**< RTC Load */
+ __IO uint32_t CTL; /**< Control */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __IO uint32_t IC; /**< Interrupt Clear */
+ __IO uint32_t RTCT; /**< RTC Trim */
+ __IO uint32_t RTCSS; /**< RTC Sub Seconds */
+ __I uint32_t RESERVED1[1]; /**< Reserved */
+ __IO uint32_t DATA; /**< Data */
+} HIB_TypeDef;
+
+/**
+ * @brief Flash Memory
+ */
+typedef struct
+{
+ __IO uint32_t FMA; /**< Flash Memory Address */
+ __IO uint32_t FMD; /**< Flash Memory Data */
+ __IO uint32_t FMC; /**< Flash Memory Control */
+ __I uint32_t FCRIS; /**< Flash Controller Raw Interrupt Status */
+ __IO uint32_t FCIM; /**< Flash Controller Interrupt Mask */
+ __IO uint32_t FCMISC; /**< Masked Interrupt Status and Clear */
+ __I uint32_t RESERVED0[2]; /**< Reserved */
+ __IO uint32_t FMC2; /**< Flash Memory Control 2 */
+ __I uint32_t RESERVED1[3]; /**< Reserved */
+ __IO uint32_t FWBVAL; /**< Flash Write Buffer Valid */
+ __I uint32_t RESERVED2[51]; /**< Reserved */
+ __IO uint32_t FWBN; /**< Flash Write Buffer n */
+ __I uint32_t RESERVED3[943]; /**< Reserved */
+ __I uint32_t FSIZE; /**< Flash Size */
+ __I uint32_t SSIZE; /**< SRAM Size */
+ __I uint32_t RESERVED4[1]; /**< Reserved */
+ __IO uint32_t ROMSWMAP; /**< ROM Software Map */
+} FLASH_TypeDef;
+
+/**
+ * @brief EEPROM Memory
+ */
+typedef struct
+{
+ __IO uint32_t EESIZE; /**< Size Information */
+ __IO uint32_t EEBLOCK; /**< Current Block */
+ __IO uint32_t EEOFFSET; /**< Current Offset */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t EERDWR; /**< Read-Write */
+ __IO uint32_t EERDWRINC; /**< Read-Write with Increment */
+ __IO uint32_t EEDONE; /**< Done Status */
+ __IO uint32_t EESUPP; /**< Support Control and Status */
+ __IO uint32_t EEUNLOCK; /**< Unlock */
+ __I uint32_t RESERVED1[3]; /**< Reserved */
+ __IO uint32_t EEPROT; /**< Protection */
+ __IO uint32_t EEPASS0; /**< Password */
+ __IO uint32_t EEPASS1; /**< Password */
+ __IO uint32_t EEPASS2; /**< Password */
+ __IO uint32_t EEINT; /**< Interrupt */
+ __I uint32_t RESERVED2[3]; /**< Reserved */
+ __IO uint32_t EEHIDE; /**< Block Hide */
+ __I uint32_t RESERVED3[11]; /**< Reserved */
+ __IO uint32_t EEDBGME; /**< Debug Mass Erase */
+ __I uint32_t RESERVED4[975]; /**< Reserved */
+ __IO uint32_t EEPROMPP; /**< Peripheral Properties */
+} EEPROM_TypeDef;
+
+/**
+ * @brief Micro Direct Memory Access
+ */
+typedef struct
+{
+ __IO uint32_t STAT; /**< Status */
+ __O uint32_t CFG; /**< Configuration */
+ __IO uint32_t CTLBASE; /**< Channel Control Base Pointer */
+ __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */
+ __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */
+ __O uint32_t SWREQ; /**< Channel Software Request */
+ __IO uint32_t USEBURSTSET; /**< Channel Useburst Set */
+ __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear */
+ __IO uint32_t REQMASKSET; /**< Channel Request Mask Set */
+ __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear */
+ __IO uint32_t ENASET; /**< Channel Enable Set */
+ __O uint32_t ENACLR; /**< Channel Enable Clear */
+ __IO uint32_t ALTSET; /**< Channel Primary Alternate Set */
+ __O uint32_t ALTCLR; /**< Channel Primary Alternate Clear */
+ __IO uint32_t PRIOSET; /**< Channel Priority Set */
+ __O uint32_t PRIOCLR; /**< Channel Priority Clear */
+ __I uint32_t RESERVED0[3]; /**< Reserved */
+ __IO uint32_t ERRCLR; /**< Bus Error Clear */
+ __I uint32_t RESERVED1[300]; /**< Reserved */
+ __IO uint32_t CHASGN; /**< Channel Assignment */
+ __IO uint32_t CHIS; /**< Channel Interrupt Status */
+ __I uint32_t RESERVED2[2]; /**< Reserved */
+ __IO uint32_t CHMAP0; /**< Channel Map Select 0 */
+ __IO uint32_t CHMAP1; /**< Channel Map Select 1 */
+ __IO uint32_t CHMAP2; /**< Channel Map Select 2 */
+ __IO uint32_t CHMAP3; /**< Channel Map Select 3 */
+} UDMA_TypeDef;
+
+/**
+ * @brief General Purpose Input/Outputs
+ */
+typedef struct
+{
+ union {
+ __IO uint32_t MASKED_ACCESS[256]; /**< Masked access of Data Register */
+ struct {
+ __I uint32_t RESERVED0[255]; /**< Reserved */
+ __IO uint32_t DATA; /**< Data */
+ };
+ };
+ __IO uint32_t DIR; /**< Direction */
+ __IO uint32_t IS; /**< Interrupt Sense */
+ __IO uint32_t IBE; /**< Interrupt Both Edges */
+ __IO uint32_t IEV; /**< Interrupt Event */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __O uint32_t ICR; /**< Interrupt Clear */
+ __IO uint32_t AFSEL; /**< Alternate Function Select */
+ __I uint32_t RESERVED1[55]; /**< Reserved */
+ __IO uint32_t DR2R; /**< 2-mA Drive Select */
+ __IO uint32_t DR4R; /**< 4-mA Drive Select */
+ __IO uint32_t DR8R; /**< 8-mA Drive Select */
+ __IO uint32_t ODR; /**< Open Drain Select */
+ __IO uint32_t PUR; /**< Pull-Up Select */
+ __IO uint32_t PDR; /**< Pull-Down Select */
+ __IO uint32_t SLR; /**< Slew Rate Control Select */
+ __IO uint32_t DEN; /**< Digital Enable */
+ __IO uint32_t LOCK; /**< Lock */
+ __IO uint32_t CR; /**< Commit */
+ __IO uint32_t AMSEL; /**< Analog Mode Select */
+ __IO uint32_t PCTL; /**< Port Control */
+ __IO uint32_t ADCCTL; /**< ADC Control */
+ __IO uint32_t DMACTL; /**< DMA Control */
+ __IO uint32_t SI; /**< */
+ __IO uint32_t DR12R; /**< */
+ __IO uint32_t WAKEPEN; /**< */
+ __IO uint32_t WAKELVL; /**< */
+ __IO uint32_t WAKESTAT; /**< */
+ __I uint32_t RESERVED2[669]; /**< */
+ __I uint32_t PP; /**< */
+ __IO uint32_t PC; /**< */
+} GPIO_TypeDef;
+
+/**
+ * @brief General Purpose Timer
+ */
+typedef struct
+{
+ __IO uint32_t CFG; /**< Configuration */
+ __IO uint32_t TAMR; /**< Timer A Mode */
+ __IO uint32_t TBMR; /**< Timer B Mode */
+ __IO uint32_t CTL; /**< Control */
+ __IO uint32_t SYNC; /**< Synchronize */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t IMR; /**< Interrupt Mask */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __O uint32_t ICR; /**< Interrupt Clear */
+ __IO uint32_t TAILR; /**< Timer A Interval Load */
+ __IO uint32_t TBILR; /**< Timer B Interval Load */
+ __IO uint32_t TAMATCHR; /**< Timer A Match */
+ __IO uint32_t TBMATCHR; /**< Timer B Match */
+ __IO uint32_t TAPR; /**< Timer A Prescale */
+ __IO uint32_t TBPR; /**< Timer B Prescale */
+ __IO uint32_t TAPMR; /**< Timer A Prescale Match */
+ __IO uint32_t TBPMR; /**< Timer B Prescale Match */
+ __I uint32_t TAR; /**< Timer A */
+ __I uint32_t TBR; /**< Timer B */
+ __IO uint32_t TAV; /**< Timer A Value */
+ __IO uint32_t TBV; /**< Timer B Value */
+ __I uint32_t RTCPD; /**< RTC Predivide */
+ __I uint32_t TAPS; /**< Timer A Prescale Snapshot */
+ __I uint32_t TBPS; /**< Timer B Prescale Snapshot */
+ __I uint32_t TAPV; /**< Timer A Prescale Value */
+ __I uint32_t TBPV; /**< Timer B Prescale Value */
+ __I uint32_t RESERVED1[981]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+} GPT_TypeDef;
+
+/**
+ * @brief Watchdog Timer
+ */
+typedef struct
+{
+ __IO uint32_t LOAD; /**< Load */
+ __I uint32_t VALUE; /**< Value */
+ __IO uint32_t CTL; /**< Control */
+ __O uint32_t ICR; /**< Interrupt Clear */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __I uint32_t RESERVED0[256]; /**< Reserved */
+ __IO uint32_t TEST; /**< Test */
+ __I uint32_t RESERVED1[505]; /**< Reserved */
+ __IO uint32_t LOCK; /**< Lock */
+} WATCHDOG_TypeDef;
+
+/**
+ * @brief Analog-to-Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t ACTSS; /**< Active Sample Sequencer */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __IO uint32_t ISC; /**< Interrupt Status and Clear */
+ __IO uint32_t OSTAT; /**< Overflow Status */
+ __IO uint32_t EMUX; /**< Event Multiplexer Select */
+ __IO uint32_t USTAT; /**< Underflow Status */
+ __IO uint32_t TSSEL; /**< Trigger Source Select */
+ __IO uint32_t SSPRI; /**< Sample Sequencer Priority */
+ __IO uint32_t SPC; /**< Sample Phase Control */
+ __IO uint32_t PSSI; /**< Processor Sample Sequence Initiate */
+ __I uint32_t RESERVED1[1]; /**< Reserved */
+ __IO uint32_t SAC; /**< Sample Averaging Control */
+ __IO uint32_t DCISC; /**< Digital Comparator Interrupt Status and
+ Clear */
+ __IO uint32_t CTL; /**< Control */
+ __I uint32_t RESERVED2[1]; /**< Reserved */
+ __IO uint32_t SSMUX0; /**< Sample Sequence Input Multiplexer Select
+ 0 */
+ __IO uint32_t SSCTL0; /**< Sample Sequence Control 0 */
+ __I uint32_t SSFIFO0; /**< Sample Sequence Result FIFO 0 */
+ __I uint32_t SSFSTAT0; /**< Sample Sequence FIFO 0 Status */
+ __IO uint32_t SSOP0; /**< Sample Sequence 0 Operation */
+ __IO uint32_t SSDC0; /**< Sample Sequence 0 Digital Comparator
+ Select */
+ __I uint32_t RESERVED3[2]; /**< Reserved */
+ __IO uint32_t SSMUX1; /**< Sample Sequence Input Multiplexer Select
+ 1 */
+ __IO uint32_t SSCTL1; /**< Sample Sequence Control 1 */
+ __I uint32_t SSFIFO1; /**< Sample Sequence Result FIFO 1 */
+ __I uint32_t SSFSTAT1; /**< Sample Sequence FIFO 1 Status */
+ __IO uint32_t SSOP1; /**< Sample Sequence 1 Operation */
+ __IO uint32_t SSDC1; /**< Sample Sequence 1 Digital Comparator
+ Select */
+ __I uint32_t RESERVED4[2]; /**< Reserved */
+ __IO uint32_t SSMUX2; /**< Sample Sequence Input Multiplexer Select
+ 2 */
+ __IO uint32_t SSCTL2; /**< Sample Sequence Control 2 */
+ __I uint32_t SSFIFO2; /**< Sample Sequence Result FIFO 2 */
+ __I uint32_t SSFSTAT2; /**< Sample Sequence FIFO 2 Status */
+ __IO uint32_t SSOP2; /**< Sample Sequence 2 Operation */
+ __IO uint32_t SSDC2; /**< Sample Sequence 2 Digital Comparator
+ Select */
+ __I uint32_t RESERVED5[2]; /**< Reserved */
+ __IO uint32_t SSMUX3; /**< Sample Sequence Input Multiplexer Select
+ 3 */
+ __IO uint32_t SSCTL3; /**< Sample Sequence Control 3 */
+ __I uint32_t SSFIFO3; /**< Sample Sequence Result FIFO 3 */
+ __I uint32_t SSFSTAT3; /**< Sample Sequence FIFO 3 Status */
+ __IO uint32_t SSOP3; /**< Sample Sequence 3 Operation */
+ __IO uint32_t SSDC3; /**< Sample Sequence 3 Digital Comparator
+ Select */
+ __I uint32_t RESERVED6[786]; /**< Reserved */
+ __O uint32_t DCRIC; /**< Digital Comparator Reset Initial
+ Conditions */
+ __I uint32_t RESERVED7[63]; /**< Reserved */
+ __IO uint32_t DCCTL0; /**< Digital Comparator Control 0 */
+ __IO uint32_t DCCTL1; /**< Digital Comparator Control 1 */
+ __IO uint32_t DCCTL2; /**< Digital Comparator Control 2 */
+ __IO uint32_t DCCTL3; /**< Digital Comparator Control 3 */
+ __IO uint32_t DCCTL4; /**< Digital Comparator Control 4 */
+ __IO uint32_t DCCTL5; /**< Digital Comparator Control 5 */
+ __IO uint32_t DCCTL6; /**< Digital Comparator Control 6 */
+ __IO uint32_t DCCTL7; /**< Digital Comparator Control 7 */
+ __I uint32_t RESERVED8[8]; /**< Reserved */
+ __IO uint32_t DCCMP0; /**< Digital Comparator Range 0 */
+ __IO uint32_t DCCMP1; /**< Digital Comparator Range 1 */
+ __IO uint32_t DCCMP2; /**< Digital Comparator Range 2 */
+ __IO uint32_t DCCMP3; /**< Digital Comparator Range 3 */
+ __IO uint32_t DCCMP4; /**< Digital Comparator Range 4 */
+ __IO uint32_t DCCMP5; /**< Digital Comparator Range 5 */
+ __IO uint32_t DCCMP6; /**< Digital Comparator Range 6 */
+ __IO uint32_t DCCMP7; /**< Digital Comparator Range 7 */
+ __I uint32_t RESERVED9[88]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+ __IO uint32_t PC; /**< Peripheral Configuration */
+ __IO uint32_t CC; /**< Clock Configuration */
+} ADC_TypeDef;
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t DR; /**< Data */
+ union {
+ __I uint32_t RSR; /**< Receive Status */
+ __O uint32_t ECR; /**< Error Clear */
+ };
+ __I uint32_t RESERVED0[4]; /**< Reserved */
+ __I uint32_t FR; /**< Flag */
+ __I uint32_t RESERVED1[1]; /**< Reserved */
+ __IO uint32_t ILPR; /**< IrDA Low-Power Register */
+ __IO uint32_t IBRD; /**< Integer Baud-Rate Divisor */
+ __IO uint32_t FBRD; /**< Fractional Baud-Rate Divisor */
+ __IO uint32_t LCRH; /**< Line Control */
+ __IO uint32_t CTL; /**< Control */
+ __IO uint32_t IFLS; /**< Interrupt FIFO Level Select */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __O uint32_t ICR; /**< Interrupt Clear */
+ __IO uint32_t DMACTL; /**< DMA Control */
+ __I uint32_t RESERVED2[22]; /**< Reserved */
+ __IO uint32_t BIT9ADDR; /**< 9-Bit Self Address */
+ __IO uint32_t BIT9AMASK; /**< 9-Bit Self Address Mask */
+ __I uint32_t RESERVED3[965]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+ __I uint32_t RESERVED4[1]; /**< Reserved */
+ __IO uint32_t CC; /**< Clock Configuration */
+} UART_TypeDef;
+
+/**
+ * @brief Synchronous Serial Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR0; /**< Control 0 */
+ __IO uint32_t CR1; /**< Control 1 */
+ __IO uint32_t DR; /**< Data */
+ __I uint32_t SR; /**< Status */
+ __IO uint32_t CPSR; /**< Clock Prescale */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __I uint32_t MIS; /**< Masked Interrupt Status */
+ __O uint32_t ICR; /**< Interrupt Clear */
+ __IO uint32_t DMACTL; /**< DMA Control */
+ __I uint32_t RESERVED1[1000];/**< Reserved */
+ __IO uint32_t CC; /**< Clock Configuration */
+} SSI_TypeDef;
+
+/**
+ * @brief Inter-Integrated Circuit
+ */
+typedef struct
+{
+ __IO uint32_t MSA; /**< Master Slave Address */
+ __IO uint32_t MCS; /**< Master Control/Status */
+ __IO uint32_t MDR; /**< Master Data */
+ __IO uint32_t MTPR; /**< Master Timer Period */
+ __IO uint32_t MIMR; /**< Master Interrupt Mask */
+ __I uint32_t MRIS; /**< Master Raw Interrupt Status */
+ __IO uint32_t MMIS; /**< Master Masked Interrupt Status */
+ __O uint32_t MICR; /**< Master Interrupt Clear */
+ __IO uint32_t MCR; /**< Master Configuration */
+ __IO uint32_t MCLKOCNT; /**< Master Clock Low Timeout Count */
+ __I uint32_t RESERVED0; /**< Reserved */
+ __I uint32_t MBMON; /**< Master Bus Monitor */
+ __IO uint32_t MCR2; /**< Master Configuration 2 */
+ __I uint32_t RESERVED1[497]; /**< Reserved */
+ __IO uint32_t SOAR; /**< Slave Own Address */
+ __IO uint32_t SCSR; /**< Slave Control/Status */
+ __IO uint32_t SDR; /**< Slave Data */
+ __IO uint32_t SIMR; /**< Slave Interrupt Mask */
+ __I uint32_t SRIS; /**< Slave Raw Interrupt Status */
+ __I uint32_t SMIS; /**< Slave Masked Interrupt Status */
+ __O uint32_t SICR; /**< Slave Interrupt Clear */
+ __IO uint32_t SOAR2; /**< Slave Own Address 2 */
+ __IO uint32_t SACKCTL; /**< Slave ACK Control */
+ __I uint32_t RESERVED2[487]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+ __I uint32_t PC; /**< Peripheral Configuration */
+} I2C_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t CTL; /**< Control */
+ __IO uint32_t STS; /**< Status */
+ __I uint32_t ERR; /**< Error Counter */
+ __IO uint32_t BIT; /**< Bit Timing */
+ __I uint32_t INT; /**< Interrupt */
+ __IO uint32_t TST; /**< Test */
+ __IO uint32_t BRPE; /**< Baud Rate Prescaler Extension */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t IF1CRQ; /**< IF1 Command Request */
+ __IO uint32_t IF1CMSK; /**< IF1 Command Mask */
+ __IO uint32_t IF1MSK1; /**< IF1 Mask 1 */
+ __IO uint32_t IF1MSK2; /**< IF1 Mask 2 */
+ __IO uint32_t IF1ARB1; /**< IF1 Arbitration 1 */
+ __IO uint32_t IF1ARB2; /**< IF1 Arbitration 2 */
+ __IO uint32_t IF1MCTL; /**< IF1 Message Control */
+ __IO uint32_t IF1DA1; /**< IF1 Data A1 */
+ __IO uint32_t IF1DA2; /**< IF1 Data A2 */
+ __IO uint32_t IF1DB1; /**< IF1 Data B1 */
+ __IO uint32_t IF1DB2; /**< IF1 Data B2 */
+ __I uint32_t RESERVED1[13]; /**< Reserved */
+ __IO uint32_t IF2CRQ; /**< IF2 Command Request */
+ __IO uint32_t IF2CMSK; /**< IF2 Command Mask */
+ __IO uint32_t IF2MSK1; /**< IF2 Mask 1 */
+ __IO uint32_t IF2MSK2; /**< IF2 Mask 2 */
+ __IO uint32_t IF2ARB1; /**< IF2 Arbitration 1 */
+ __IO uint32_t IF2ARB2; /**< IF2 Arbitration 2 */
+ __IO uint32_t IF2MCTL; /**< IF2 Message Control */
+ __IO uint32_t IF2DA1; /**< IF2 Data A1 */
+ __IO uint32_t IF2DA2; /**< IF2 Data A2 */
+ __IO uint32_t IF2DB1; /**< IF2 Data B1 */
+ __IO uint32_t IF2DB2; /**< IF2 Data B2 */
+ __I uint32_t RESERVED2[21]; /**< Reserved */
+ __I uint32_t TXRQ1; /**< Transmission Request 1 */
+ __I uint32_t TXRQ2; /**< Transmission Request 2 */
+ __I uint32_t RESERVED3[6]; /**< Reserved */
+ __I uint32_t NWDA1; /**< New Data 1 */
+ __I uint32_t NWDA2; /**< New Data 2 */
+ __I uint32_t RESERVED4[6]; /**< Reserved */
+ __I uint32_t MSG1INT; /**< Message 1 Interrupt Pending */
+ __I uint32_t MSG2INT; /**< Message 2 Interrupt Pending */
+ __I uint32_t RESERVED5[6]; /**< Reserved */
+ __I uint32_t MSG1VAL; /**< Message 1 Valid */
+ __I uint32_t MSG2VAL; /**< Message 2 Valid */
+} CAN_TypeDef;
+
+// USB
+
+/**
+ * @brief Analog Comparator
+ */
+typedef struct
+{
+ __IO uint32_t MIS; /**< Masked Interrupt Status */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t INTEN; /**< Interrupt Enable */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t REFCTL; /**< Reference Voltage Control */
+ __I uint32_t RESERVED1[3]; /**< Reserved */
+ __I uint32_t STAT0; /**< Status 0 */
+ __IO uint32_t CTL0; /**< Control 0 */
+ __I uint32_t RESERVED2[6]; /**< Reserved */
+ __I uint32_t STAT1; /**< Status 1 */
+ __IO uint32_t CTL1; /**< Control 1 */
+ __I uint32_t RESERVED3[990]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+} AC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CTL; /**< Control */
+ __IO uint32_t INTEN; /**< Interrupt and Trigger Enable */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t ISC; /**< Interrupt Status and Clear */
+ __IO uint32_t LOAD; /**< Load */
+ __I uint32_t COUNT; /**< Counter */
+ __IO uint32_t CMP[2]; /**< Compare A, B */
+ __IO uint32_t GEN[2]; /**< Generator A, B Control */
+ __IO uint32_t DBCTL; /**< Dead-Band Control */
+ __IO uint32_t DBRISE; /**< Dead-Band Rising-Edge Delay */
+ __IO uint32_t DBFALL; /**< Dead-Band Falling-Edge Delay */
+ __IO uint32_t FLTSRC[2]; /**< Fault Source 0, 1 */
+ __IO uint32_t MINFLTPER; /**< Minimum Fault Period */
+} PWM_GENERATOR_T;
+
+/*
+ * @brief Pulse Width Modulator
+ */
+typedef struct
+{
+ __IO uint32_t CTL; /**< Master Control */
+ __IO uint32_t SYNC; /**< Time Base Sync */
+ __IO uint32_t ENABLE; /**< Output Enable */
+ __IO uint32_t INVERT; /**< Output Inversion */
+ __IO uint32_t FAULT; /**< Output Fault */
+ __IO uint32_t INTEN; /**< Interrupt Enable */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t ISC; /**< Interrupt Status and Clear */
+ __I uint32_t STATUS; /**< Status */
+ __IO uint32_t FAULTVAL; /**< Fault Condition Value */
+ __IO uint32_t ENUPD; /**< Enable Update */
+ __I uint32_t RESERVED0[5]; /**< Reserved */
+ __IO PWM_GENERATOR_T PWM[4]; /**< PWM Generator 0, 1, 2 and 3 */
+ __I uint32_t RESERVED1[432]; /**< Reserved */
+ __IO uint32_t _0FLTSEN; /**< Fault Pin Logic Sense */
+ __IO uint32_t _0FLTSTAT[2]; /**< Fault Status 0, 1 */
+ __I uint32_t RESERVED2[29]; /**< Reserved */
+ __IO uint32_t _1FLTSEN; /**< Fault Pin Logic Sense */
+ __IO uint32_t _1FLSTSAT[2]; /**< Fault Status 0, 1 */
+ __I uint32_t RESERVED3[30]; /**< Reserved */
+ __IO uint32_t _2FLTSTAT[2]; /**< Fault Status 0, 1 */
+ __I uint32_t RESERVED4[30]; /**< Reserved */
+ __IO uint32_t _3FLTSTAT[2]; /**< Fault Status 0, 1 */
+ __I uint32_t RESERVED5[397]; /**< Reserved */
+ __I uint32_t PP; /**< Peripheral Properties */
+ __IO uint32_t CC; /**< Clock Configuration */
+} PWM_TypeDef;
+
+/**
+ * @brief Quadrature Encoder Interface
+ */
+typedef struct
+{
+ __IO uint32_t CTL; /**< Control */
+ __I uint32_t STAT; /**< Status */
+ __IO uint32_t POS; /**< Position */
+ __IO uint32_t MAXPOS; /**< Maximum Position */
+ __IO uint32_t LOAD; /**< Timer Load */
+ __I uint32_t TIME; /**< Timer */
+ __I uint32_t COUNT; /**< Velocity Counter */
+ __I uint32_t SPEED; /**< Velocity */
+ __IO uint32_t INTEN; /**< Interrupt Enable */
+ __I uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t ISC; /**< Interrupt Status and Clear */
+} QEI_TypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup Peripheral_memorymap
+ * @{
+ */
+
+#define SYSCTL_BASE 0x400FE000
+#define HIB_BASE 0x400FC000
+#define FLASH_BASE 0x400FD000
+#define EEPROM_BASE 0x400AF000
+#define UDMA_BASE 0x400FF000
+#define GPIOA_BASE 0x40058000
+#define GPIOB_BASE 0x40059000
+#define GPIOC_BASE 0x4005A000
+#define GPIOD_BASE 0x4005B000
+#define GPIOE_BASE 0x4005C000
+#define GPIOF_BASE 0x4005D000
+#define GPIOG_BASE 0x4005E000
+#define GPIOH_BASE 0x4005F000
+#define GPIOJ_BASE 0x40060000
+#define GPIOK_BASE 0x40061000
+#define GPIOL_BASE 0x40062000
+#define GPIOM_BASE 0x40063000
+#define GPION_BASE 0x40064000
+#define GPIOP_BASE 0x40065000
+#define GPIOQ_BASE 0x40066000
+#define GPT0_BASE 0x40030000
+#define GPT1_BASE 0x40031000
+#define GPT2_BASE 0x40032000
+#define GPT3_BASE 0x40033000
+#define GPT4_BASE 0x40034000
+#define GPT5_BASE 0x40035000
+#define WGPT0_BASE 0x40036000
+#define WGPT1_BASE 0x40037000
+#define WGPT2_BASE 0x4004C000
+#define WGPT3_BASE 0x4004D000
+#define WGPT4_BASE 0x4004E000
+#define WGPT5_BASE 0x4004F000
+#define WDT0_BASE 0x40000000
+#define WDT1_BASE 0x40001000
+#define ADC0_BASE 0x40038000
+#define ADC1_BASE 0x40039000
+#define UART0_BASE 0x4000C000
+#define UART1_BASE 0x4000D000
+#define UART2_BASE 0x4000E000
+#define UART3_BASE 0x4000F000
+#define UART4_BASE 0x40010000
+#define UART5_BASE 0x40011000
+#define UART6_BASE 0x40012000
+#define UART7_BASE 0x40013000
+#define SSI0_BASE 0x40008000
+#define SSI1_BASE 0x40009000
+#define SSI2_BASE 0x4000A000
+#define SSI3_BASE 0x4000B000
+#define I2C0_BASE 0x40020000
+#define I2C1_BASE 0x40021000
+#define I2C2_BASE 0x40022000
+#define I2C3_BASE 0x40023000
+#define CAN0_BASE 0x40040000
+#define CAN1_BASE 0x40041000
+// usb
+#define AC_BASE 0x4003C000
+#define PWM0_BASE 0x40028000
+#define QEI0_BASE 0x4002C000
+#define QEI1_BASE 0x4002D000
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE)
+#define HIB ((HIB_TypeDef *) HIB_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
+#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE)
+#define UDMA ((UDMA_TypeDef *) UDMA_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define GPIOL ((GPIO_TypeDef *) GPIOL_BASE)
+#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE)
+#define GPION ((GPIO_TypeDef *) GPION_BASE)
+#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE)
+#define GPIOQ ((GPIO_TypeDef *) GPIOQ_BASE)
+#define GPT0 ((GPT_TypeDef *) GPT0_BASE)
+#define GPT1 ((GPT_TypeDef *) GPT1_BASE)
+#define GPT2 ((GPT_TypeDef *) GPT2_BASE)
+#define GPT3 ((GPT_TypeDef *) GPT3_BASE)
+#define GPT4 ((GPT_TypeDef *) GPT4_BASE)
+#define GPT5 ((GPT_TypeDef *) GPT5_BASE)
+#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE)
+#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE)
+#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE)
+#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE)
+#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE)
+#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE)
+#define ADC0 ((ADC_TypeDef*) ADC0_BASE)
+#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
+#define UART0 ((UART_TypeDef *) UART0_BASE)
+#define UART1 ((UART_TypeDef *) UART1_BASE)
+#define UART2 ((UART_TypeDef *) UART2_BASE)
+#define UART3 ((UART_TypeDef *) UART3_BASE)
+#define UART4 ((UART_TypeDef *) UART4_BASE)
+#define UART5 ((UART_TypeDef *) UART5_BASE)
+#define UART6 ((UART_TypeDef *) UART6_BASE)
+#define UART7 ((UART_TypeDef *) UART7_BASE)
+#define SSI0 ((SSI_TypeDef *) SSI0_BASE)
+#define SSI1 ((SSI_TypeDef *) SSI1_BASE)
+#define SSI2 ((SSI_TypeDef *) SSI2_BASE)
+#define SSI3 ((SSI_TypeDef *) SSI3_BASE)
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN0 ((CAN_TypeDef *) CAN0_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+// usb
+#define AC ((AC_TypeDef *) AC_BASE)
+#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
+#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
+#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
+
+/**
+ * @}
+ */
+
+#endif /* __TM4C129x_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 14:53:42 +0000