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author | Michael Walker <walkerstop@gmail.com> | 2018-05-02 03:37:31 -0700 |
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committer | Michael Walker <walkerstop@gmail.com> | 2018-05-02 03:37:31 -0700 |
commit | cd7559268dcc2da5f2b1f3872e6baa1cff1d5476 (patch) | |
tree | 0cf31de069f9df06a13743eab4e1879f05ce9c12 /os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2 | |
parent | 4d7ccdd1fce0c95c57129b80c81fab829daf9f99 (diff) | |
parent | 457afa6202fe9f8e6accb65411629172bb32c41b (diff) | |
download | ChibiOS-Contrib-cd7559268dcc2da5f2b1f3872e6baa1cff1d5476.tar.gz ChibiOS-Contrib-cd7559268dcc2da5f2b1f3872e6baa1cff1d5476.tar.bz2 ChibiOS-Contrib-cd7559268dcc2da5f2b1f3872e6baa1cff1d5476.zip |
Merge branch 'master' into mike
Diffstat (limited to 'os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2')
-rw-r--r-- | os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c | 189 | ||||
-rw-r--r-- | os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h | 18 |
2 files changed, 175 insertions, 32 deletions
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c index e6c6080..09b44f7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c @@ -14,45 +14,197 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; -#if HAL_USE_PAL || defined(__DOXYGEN__) /** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. + * @brief STM32 GPIO static initialization data. */ -const PALConfig pal_default_config = -{ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif }; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); #endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ /** * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { + stm32_gpio_init(); stm32_clock_init(); } @@ -60,21 +212,21 @@ void __early_init(void) { /** * @brief SDC card detection. */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief SDC card write protection detection. */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif /* HAL_USE_SDC */ @@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { /** * @brief MMC_SPI card detection. */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief MMC_SPI card write protection detection. */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif @@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any. */ void boardInit(void) { + } diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index 05aeceb..0788eb7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -587,19 +587,14 @@ PIN_OSPEED_100M(GPIOD_MEM_D0) | \ PIN_OSPEED_100M(GPIOD_MEM_D1)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#else -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#endif #define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \ - NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ + PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\ + PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \ @@ -893,21 +888,16 @@ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#else -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#endif #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \ - NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) | \ PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \ |