diff options
Diffstat (limited to 'async_16bit_bus_adapter_hw')
| -rw-r--r-- | async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl | 7 | ||||
| -rw-r--r-- | async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd | 10 |
2 files changed, 9 insertions, 8 deletions
diff --git a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl index d18a0ed..08709ff 100644 --- a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl +++ b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 19:47:04 BST 2013 +# Mon Oct 14 20:08:19 BST 2013 # DO NOT MODIFY # # async_16bit_bus_adapter "async_16bit_bus_adapter" v1.0 -# 2013.10.14.19:47:04 +# 2013.10.14.20:08:19 # # @@ -85,6 +85,7 @@ set_interface_property avalon_slave burstOnBurstBoundariesOnly false set_interface_property avalon_slave burstcountUnits WORDS set_interface_property avalon_slave explicitAddressSpan 0 set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave isMemoryDevice true set_interface_property avalon_slave linewrapBursts false set_interface_property avalon_slave maximumPendingReadTransactions 0 set_interface_property avalon_slave readLatency 0 @@ -105,7 +106,7 @@ add_interface_port avalon_slave rd_n read_n Input 1 add_interface_port avalon_slave wait_n waitrequest_n Output 1 add_interface_port avalon_slave readdata readdata Output 16 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 -set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 1 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 diff --git a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd index 9c8a806..715123f 100644 --- a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd +++ b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd @@ -1,4 +1,4 @@ --- async_8bit_bus_adapter.vhd +-- async_16bit_bus_adapter.vhd -- This file was auto-generated as a prototype implementation of a module -- created in component editor. It ties off all outputs to ground and @@ -12,7 +12,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -entity async_8bit_bus_adapter is +entity async_16bit_bus_adapter is generic ( AUTO_CLOCK_CLOCK_RATE : string := "-1" ); @@ -34,9 +34,9 @@ entity async_8bit_bus_adapter is b_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- .export b_data_out : out std_logic_vector(15 downto 0) -- .export ); -end entity async_8bit_bus_adapter; +end entity async_16bit_bus_adapter; -architecture rtl of async_8bit_bus_adapter is +architecture rtl of async_16bit_bus_adapter is signal state:std_logic_vector(2 downto 0); begin @@ -51,4 +51,4 @@ begin wait_n <= b_wait_n; -end architecture rtl; -- of async_8bit_bus_adapter +end architecture rtl; -- of async_16bit_bus_adapter |