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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sdram is
port (
clock_50 : in std_logic;
DI : in std_logic_vector(6 downto 0);
fish : out std_logic;
);
end entity;
architecture rtl of saa5050 is
begin
fish <= clock_50;
end architecture;
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