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| author | James <james.mckenzie@citrix.com> | 2013-10-14 15:17:08 +0100 |
|---|---|---|
| committer | James <james.mckenzie@citrix.com> | 2013-10-14 15:17:08 +0100 |
| commit | dee10e9511e5d21ae1c4c02b6b786850b3013b88 (patch) | |
| tree | 47d0f7dce19fe8b7d44ce74129beb1a5d79d10fa /async_8bit_bus_adapter_hw | |
| parent | 72b35b0e4d9f08c4f69d40beae04da1cc8df3c9d (diff) | |
| download | sdram-dee10e9511e5d21ae1c4c02b6b786850b3013b88.tar.gz sdram-dee10e9511e5d21ae1c4c02b6b786850b3013b88.tar.bz2 sdram-dee10e9511e5d21ae1c4c02b6b786850b3013b88.zip | |
fish
Diffstat (limited to 'async_8bit_bus_adapter_hw')
3 files changed, 8 insertions, 13 deletions
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl index d4b4688..0b52d75 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:03:03 BST 2013 +# Mon Oct 14 15:16:40 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:03:03 +# 2013.10.14.15:16:40 # # @@ -133,8 +133,7 @@ set_interface_property eight_bit_bus PORT_NAME_MAP "" set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" add_interface_port eight_bit_bus b_cs_n export Output 1 -add_interface_port eight_bit_bus b_rd_n export Output 1 -add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_rnw export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ index 5171d01..19ea7ae 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:01:25 BST 2013 +# Mon Oct 14 15:03:03 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:01:25 +# 2013.10.14.15:03:03 # # @@ -133,8 +133,7 @@ set_interface_property eight_bit_bus PORT_NAME_MAP "" set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" add_interface_port eight_bit_bus b_cs_n export Output 1 -add_interface_port eight_bit_bus b_rd_n export Output 1 -add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_rnw export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd index 29e4ff3..14c45e7 100644 --- a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd +++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd @@ -27,8 +27,7 @@ entity async_8bit_bus_adapter is wait_n : out std_logic; -- .waitrequest_n readdata : out std_logic_vector(7 downto 0); -- .readdata b_cs_n : out std_logic; -- eight_bit_bus.export - b_rd_n : out std_logic; -- .export - b_wr_n : out std_logic; -- .export + b_rnw : out std_logic; -- .export b_wait_n : in std_logic := '0'; -- .export b_addr : out std_logic_vector(15 downto 0); -- .export b_data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export @@ -45,9 +44,7 @@ begin b_cs_n <= '0'; - b_wr_n <= '0'; - - b_rd_n <= '0'; + b_rnw <= '0'; b_data_out <= "00000000"; |