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authorJames <james.mckenzie@citrix.com>2013-10-14 19:06:11 +0100
committerJames <james.mckenzie@citrix.com>2013-10-14 19:06:11 +0100
commit16af4b953306063c2aed52ab2ecde07e0bc6b5e4 (patch)
tree83839ec3e3308396a22576ffeac5a4b7cce6bf26 /async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
parent3b79402993f7857243ab033644d7ca6b757be76d (diff)
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works!
Diffstat (limited to 'async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd')
-rw-r--r--async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd21
1 files changed, 11 insertions, 10 deletions
diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
index 14c45e7..c48663f 100644
--- a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
+++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
@@ -26,7 +26,8 @@ entity async_8bit_bus_adapter is
rd_n : in std_logic := '0'; -- .read_n
wait_n : out std_logic; -- .waitrequest_n
readdata : out std_logic_vector(7 downto 0); -- .readdata
- b_cs_n : out std_logic; -- eight_bit_bus.export
+ b_reset_n : out std_logic; -- eight_bit_bus.export
+ b_cs_n : out std_logic; -- .export
b_rnw : out std_logic; -- .export
b_wait_n : in std_logic := '0'; -- .export
b_addr : out std_logic_vector(15 downto 0); -- .export
@@ -36,18 +37,18 @@ entity async_8bit_bus_adapter is
end entity async_8bit_bus_adapter;
architecture rtl of async_8bit_bus_adapter is
-begin
-
- -- TODO: Auto-generated HDL template
- readdata <= "00000000";
-
- b_cs_n <= '0';
+signal state:std_logic_vector(2 downto 0);
+begin
- b_rnw <= '0';
+ b_addr <= address;
+ readdata <= b_data_in;
+ b_data_out <= writedata;
- b_data_out <= "00000000";
+ b_reset_n <= rst_n;
+ b_cs_n <= cs_n or ( wr_n and rd_n );
+ b_rnw <= wr_n;
+ wait_n <= b_wait_n;
- b_addr <= "0000000000000000";
end architecture rtl; -- of async_8bit_bus_adapter