remove-path

2 files changed, 357 insertions, 0 deletions

diff --git a/GPU/gpu_hw.tcl b/GPU/gpu_hw.tcl
new file mode 100644
index 0000000..5eae01e
--- /dev/null
+++ b/GPU/gpu_hw.tcl
@@ -0,0 +1,138 @@
+# TCL File Generated by Component Editor 13.0sp1
+# Wed Oct 09 17:56:27 BST 2013
+# DO NOT MODIFY
+
+
+# 
+# gpu "gpu" v1.0
+#  2013.10.09.17:56:27
+# 
+# 
+
+# 
+# request TCL package from ACDS 13.1
+# 
+package require -exact qsys 13.1
+
+
+# 
+# module gpu
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME gpu
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP my_lib
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME gpu
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL AUTO
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL gpuv2
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file GPU_IF.v VERILOG PATH hdl/GPU_IF.v
+
+add_fileset SIM_VHDL SIM_VHDL "" ""
+set_fileset_property SIM_VHDL TOP_LEVEL gpuv2
+set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file gpu_hw.tcl OTHER PATH gpu_hw.tcl
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset rst_n reset_n Input 1
+
+
+# 
+# connection point vga
+# 
+add_interface vga conduit end
+set_interface_property vga associatedClock ""
+set_interface_property vga associatedReset ""
+set_interface_property vga ENABLED true
+set_interface_property vga EXPORT_OF ""
+set_interface_property vga PORT_NAME_MAP ""
+set_interface_property vga SVD_ADDRESS_GROUP ""
+
+add_interface_port vga vga_red export Output 3
+add_interface_port vga vga_green export Output 3
+add_interface_port vga vga_blue export Output 3
+add_interface_port vga vga_hs export Output 1
+add_interface_port vga vga_vs export Output 1
+add_interface_port vga vga_clk export Input 1
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave cs_n chipselect_n Input 1
+add_interface_port avalon_slave address address Input 7
+add_interface_port avalon_slave data writedata Input 32
+add_interface_port avalon_slave wr_n write_n Input 1
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+
diff --git a/GPU/hdl/GPU_IF.v b/GPU/hdl/GPU_IF.v
new file mode 100644
index 0000000..f32de1e
--- /dev/null
+++ b/GPU/hdl/GPU_IF.v
@@ -0,0 +1,219 @@
+// gpuv2.v
+
+// This file was auto-generated as a prototype implementation of a module
+// created in component editor.  It ties off all outputs to ground and
+// ignores all inputs.  It needs to be edited to make it do something
+// useful.
+// 
+// This file will not be automatically regenerated.  You should check it in
+// to your version control system if you want to keep it.
+
+`timescale 1 ps / 1 ps
+module gpuv2 #(
+		parameter AUTO_CLOCK_CLOCK_RATE = "-1"
+	) (
+		input  wire       clk,       //        clock.clk
+		input  wire       rst_n,     //        reset.reset_n
+		input  wire       vga_clk,   //      vga_out.export
+		output reg [2:0] vga_red,    //             .export
+		output reg [2:0] vga_green,  //             .export
+		output reg [2:0] vga_blue,   //             .export
+		output reg        vga_hs,    //             .export
+		output reg        vga_vs,    //             .export
+		input  wire [31:0] data,     // avalon_slave.writedata
+		input  wire       wr_n,      //             .write_n
+		input  wire       cs_n,      //             .chipselect_n
+		input  wire [6:0] address    //             .address
+	);
+
+
+  reg [9:0] ball_x;
+  reg [8:0] ball_y;
+  reg [8:0] bat0_y;
+  reg [8:0] bat1_y;
+
+  reg [15:0] sprite[0:15];
+  
+  wire [4:0] reg_addr;
+ 
+  assign reg_addr = address[6:2];
+  
+  
+  reg [2:0] sprite_red;
+  reg [2:0] sprite_green;
+  reg [2:0] sprite_blue;
+  
+  always @(posedge clk or negedge rst_n)
+  begin
+	if (rst_n == 0) begin
+			ball_x <= 10'd127;
+			ball_y <= 10'd127;
+			bat0_y <= 10'd100;
+			bat1_y <= 10'd200;
+			
+			sprite[0]=16'b1111111111111111;
+			sprite[1]=16'b1000000000000001;
+			sprite[2]=16'b1000000000000001;
+			sprite[3]=16'b1000000000000001;
+			sprite[4]=16'b1000000000000001;
+			sprite[5]=16'b1000000000000001;
+			sprite[6]=16'b1000000000000001;
+			sprite[7]=16'b1000000000000001;
+			sprite[8]=16'b1000000000000001;
+			sprite[9]=16'b1000000000000001;
+			sprite[10]=16'b1000000000000001;
+			sprite[11]=16'b1000000000000001;
+			sprite[12]=16'b1000000000000001;
+			sprite[13]=16'b1000000000000001;
+			sprite[14]=16'b1000000000000001;
+			sprite[15]=16'b1111111111111111;
+			
+			sprite_red[2:0]=3'b111;
+			sprite_green[2:0]=3'b000;
+			sprite_blue[2:0]=3'b111;
+			
+	end else if (~cs_n && ~wr_n) begin
+		if (reg_addr[4]) begin
+			sprite[reg_addr[3:0]]<=data[15:0];
+		end else begin
+			case (reg_addr[2:0]) 
+				3'b000:
+					ball_x <= data[9:0];
+				3'b001:
+					ball_y <= data[8:0];
+				3'b010:
+					bat0_y <= data[8:0];
+				3'b011:
+					bat1_y <= data[8:0];
+				3'b100:
+					begin
+						sprite_red <= data[8:6];
+						sprite_green <= data[5:3];
+						sprite_blue <= data[2:0];
+					end
+			endcase
+		end
+	end
+  end
+
+
+  reg trig_25M;
+  always @ (posedge vga_clk)
+  begin
+    if(!rst_n)
+      trig_25M <= 1'b0;
+    else
+      trig_25M <= ~trig_25M;
+  end 
+  
+  reg [9:0] vector_x;
+  always @ (posedge vga_clk or negedge rst_n)
+  begin
+    if(!rst_n)
+      vector_x <= 10'd0;
+    else if(trig_25M)
+      begin
+        if(vector_x != 10'd799)
+          vector_x <= vector_x + 1'b1;
+        else
+          vector_x <= 10'd0;
+      end
+  end 
+  
+  reg [9:0] vector_y;
+  always @ (posedge vga_clk or negedge rst_n)
+  begin
+    if(!rst_n)
+      vector_y <= 10'd0;
+    else if(trig_25M)
+      begin
+        if(vector_x == 10'd799)
+          begin
+            if(vector_y != 10'd524)
+              vector_y <= vector_y + 1'b1;
+            else
+              vector_y <= 10'd0;
+          end
+      end
+  end
+  
+  always @ (posedge vga_clk or negedge rst_n)
+  begin
+    if(!rst_n)
+      vga_hs <= 1'b0;
+    else if(trig_25M)
+      begin
+        if(vector_x >= 10'd656 && vector_x < 10'd752)
+          vga_hs <= 1'b0;
+        else
+          vga_hs <= 1'b1;
+      end
+  end
+  
+  always @ (posedge vga_clk or negedge rst_n)
+  begin
+    if(!rst_n)
+      vga_vs <= 1'b0;
+    else if(trig_25M)
+      begin
+        if(vector_y >= 10'd490 && vector_y < 10'd492)
+          vga_vs <= 1'b0;
+        else
+          vga_vs <= 1'b1;
+      end
+  end
+  
+  
+  
+  reg [2:0] index;
+  always @ (posedge vga_clk or negedge rst_n)
+  begin
+    if(!rst_n)
+      index <= 3'b000;
+    else if(trig_25M)
+      begin
+        if(vector_x < 10'd640 && vector_y < 10'd480) 
+		  if(vector_x >= (ball_x - 8 )&& vector_x <=( ball_x + 7 )
+				&& vector_y >= (ball_y - 8) && vector_y <= (ball_y + 7)) begin 
+				if (sprite[(vector_y - (ball_y - 8)) & 15 ][(vector_x - (ball_x -8))& 15 ])
+					index <= 3'b001;
+				else
+					index <= 3'b000;
+		  end else if (vector_x  < 10'd4) 
+				if (vector_y >=( bat0_y - 20 ) && vector_y <= (bat0_y + 20) )
+					index <= 3'b111;
+				else
+					index <= 3'b000;
+		  else if (vector_x >= 10'd318 && vector_x < 10'd322)
+			  index <= {3{vector_y[3]}};
+		  else if (vector_x >= 10'd636 && vector_x < 10'd640)
+				if (vector_y >=( bat1_y - 20 ) && vector_y <= (bat1_y + 20) )
+					index <= 3'b111;
+				else
+					index <= 3'b000;
+		  else
+          		index <= 3'b000;
+	else
+          index <= 3'b000;
+     end
+  end
+  
+  always begin
+	if (index == 3'b000) begin
+		vga_red = 3'b000;
+		vga_green = 3'b000;
+		vga_blue = 3'b000;
+	end else if (index == 3'b001) begin
+		vga_red = sprite_red;
+		vga_green= sprite_green;
+		vga_blue = sprite_blue;
+	end else begin
+		vga_red= 3'b111;
+		vga_green=3'b111;
+		vga_blue=3'b111;
+	end
+		
+  
+  end
+  
+endmodule