diff options
Diffstat (limited to 'GPU/gpu_hw.tcl')
| -rw-r--r-- | GPU/gpu_hw.tcl | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/GPU/gpu_hw.tcl b/GPU/gpu_hw.tcl new file mode 100644 index 0000000..5eae01e --- /dev/null +++ b/GPU/gpu_hw.tcl @@ -0,0 +1,138 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Wed Oct 09 17:56:27 BST 2013 +# DO NOT MODIFY + + +# +# gpu "gpu" v1.0 +# 2013.10.09.17:56:27 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module gpu +# +set_module_property DESCRIPTION "" +set_module_property NAME gpu +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME gpu +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL gpuv2 +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file GPU_IF.v VERILOG PATH hdl/GPU_IF.v + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL gpuv2 +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file gpu_hw.tcl OTHER PATH gpu_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point vga +# +add_interface vga conduit end +set_interface_property vga associatedClock "" +set_interface_property vga associatedReset "" +set_interface_property vga ENABLED true +set_interface_property vga EXPORT_OF "" +set_interface_property vga PORT_NAME_MAP "" +set_interface_property vga SVD_ADDRESS_GROUP "" + +add_interface_port vga vga_red export Output 3 +add_interface_port vga vga_green export Output 3 +add_interface_port vga vga_blue export Output 3 +add_interface_port vga vga_hs export Output 1 +add_interface_port vga vga_vs export Output 1 +add_interface_port vga vga_clk export Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 7 +add_interface_port avalon_slave data writedata Input 32 +add_interface_port avalon_slave wr_n write_n Input 1 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + |