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authorJames <james.mckenzie@citrix.com>2013-10-18 12:19:09 +0100
committerJames <james.mckenzie@citrix.com>2013-10-18 12:19:09 +0100
commitd8b2c4c49c778a36d306ee02b7fefe53a4cbb32c (patch)
tree3d962748e9d7bea2e10c978ce833091ece6168dc /quartus/mc6845.vhd
parent3c24b4b41abf56cfd3cdcd998b77514d9ba55a6c (diff)
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Revert "revert fixes"
This reverts commit 3c24b4b41abf56cfd3cdcd998b77514d9ba55a6c.
Diffstat (limited to 'quartus/mc6845.vhd')
-rw-r--r--quartus/mc6845.vhd13
1 files changed, 7 insertions, 6 deletions
diff --git a/quartus/mc6845.vhd b/quartus/mc6845.vhd
index 31208ea..5abbbd2 100644
--- a/quartus/mc6845.vhd
+++ b/quartus/mc6845.vhd
@@ -70,6 +70,7 @@ port (
);
end entity;
+-- altera message_off 10036
architecture rtl of mc6845 is
-- Host-accessible registers
@@ -231,7 +232,7 @@ begin
end process; -- registers
-- Horizontal, vertical and address counters
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable ma_row_start : unsigned(13 downto 0);
variable max_scan_line : unsigned(4 downto 0);
begin
@@ -318,7 +319,7 @@ begin
-- Signals to mark hsync and half way points for generating
-- vsync in even and odd fields
- process(h_counter)
+ process(h_counter,r02_h_sync_pos)
begin
h_sync_start <= '0';
h_half_way <= '0';
@@ -332,7 +333,7 @@ begin
end process;
-- Video timing and sync counters
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
-- H
@@ -399,7 +400,7 @@ begin
end process;
-- Address generation
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable slv_line : std_logic_vector(4 downto 0);
begin
if nRESET = '0' then
@@ -423,7 +424,7 @@ begin
end process;
-- Cursor control
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable cursor_line : std_logic;
begin
-- Internal cursor enable signal delayed by 1 clock to line up
@@ -459,7 +460,7 @@ begin
end process;
-- Light pen capture
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
lpstb_i <= '0';