Revert "revert fixes"

This reverts commit 3c24b4b41abf56cfd3cdcd998b77514d9ba55a6c.

9 files changed, 28 insertions, 25 deletions

diff --git a/quartus/T65/T65.vhd b/quartus/T65/T65.vhd
index 4a21d79..b803cce 100644
--- a/quartus/T65/T65.vhd
+++ b/quartus/T65/T65.vhd
@@ -94,6 +94,7 @@ entity T65 is
 	);

 end T65;

 

+-- altera message_off 10036

 architecture rtl of T65 is

 

 	-- Registers

diff --git a/quartus/bbc_micro_de1.qsf b/quartus/bbc_micro_de1.qsf
index e8a19c8..1f4e73f 100644
--- a/quartus/bbc_micro_de1.qsf
+++ b/quartus/bbc_micro_de1.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP2C20F484C7
 set_global_assignment -name TOP_LEVEL_ENTITY bbc_micro_de1

 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1

 set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:48:44  JULY 12, 2011"

-set_global_assignment -name LAST_QUARTUS_VERSION 9.1

+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484

@@ -535,4 +535,4 @@ set_global_assignment -name VHDL_FILE keyboard.vhd
 set_global_assignment -name VHDL_FILE debugger.vhd

 set_global_assignment -name QIP_FILE saa5050_rom.qip

 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/quartus/bbc_micro_de1.vhd b/quartus/bbc_micro_de1.vhd
index d78fe69..080b390 100644
--- a/quartus/bbc_micro_de1.vhd
+++ b/quartus/bbc_micro_de1.vhd
@@ -987,7 +987,7 @@ begin
 		end if;

 	end process;

 	

-	cycle_stretch: process(clock,reset_n)

+	cycle_stretch: process(clock,reset_n,mhz2_clken)

 	begin

 		if reset_n = '0' then

 			cpu_cycle_mask <= '0';

@@ -1145,7 +1145,7 @@ begin
 	SRAM_DQ(15 downto 8) <= (others => '0');

 	

 	-- Synchronous outputs to SRAM

-	process(clock,reset_n)

+	process(clock,reset_n,ram_enable,cpu_r_nw)

 	variable ram_write : std_logic;

 	begin		

 		ram_write := ram_enable and not cpu_r_nw;

@@ -1284,7 +1284,7 @@ begin
 	caps_lock_led_n <= ic32(6);

 	shift_lock_led_n <= ic32(7);

 	

-	process(clock,reset_n)

+	process(clock,reset_n,sys_via_pb_out)

 	variable bit_num : integer;

 	begin

 		bit_num := to_integer(unsigned(sys_via_pb_out(2 downto 0)));

diff --git a/quartus/debugger.vhd b/quartus/debugger.vhd
index 1d78bd5..d4dfe61 100644
--- a/quartus/debugger.vhd
+++ b/quartus/debugger.vhd
@@ -213,7 +213,7 @@ begin
 	end process;

 	

 	-- Set watchpoint address

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,mode)

 	begin

 		if nRESET = '0' then

 			watchpoint <= (others => '1');

@@ -232,7 +232,7 @@ begin
 	end process;

 	

 	-- Set breakpoint address

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,mode)

 	begin

 		if nRESET = '0' then

 			breakpoint <= (others => '1');

diff --git a/quartus/i2c_loader.vhd b/quartus/i2c_loader.vhd
index 35da643..4b3343c 100644
--- a/quartus/i2c_loader.vhd
+++ b/quartus/i2c_loader.vhd
@@ -132,7 +132,7 @@ begin
 	end process;

 

 	-- The I2C loader process

-	process(nRESET,CLK)

+	process(nRESET,CLK,clken)

 	begin

 		if nRESET = '0' then

 			scl_out <= '1';

diff --git a/quartus/mc6845.vhd b/quartus/mc6845.vhd
index 31208ea..5abbbd2 100644
--- a/quartus/mc6845.vhd
+++ b/quartus/mc6845.vhd
@@ -70,6 +70,7 @@ port (
 	);

 end entity;

 

+-- altera message_off 10036
 architecture rtl of mc6845 is

 

 -- Host-accessible registers

@@ -231,7 +232,7 @@ begin
 	end process; -- registers

 	

 	-- Horizontal, vertical and address counters

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	variable ma_row_start : unsigned(13 downto 0);

 	variable max_scan_line : unsigned(4 downto 0);

 	begin

@@ -318,7 +319,7 @@ begin
 	

 	-- Signals to mark hsync and half way points for generating

 	-- vsync in even and odd fields

-	process(h_counter)

+	process(h_counter,r02_h_sync_pos)

 	begin

 		h_sync_start <= '0';

 		h_half_way <= '0';

@@ -332,7 +333,7 @@ begin
 	end process;

 	

 	-- Video timing and sync counters

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin

 		if nRESET = '0' then

 			-- H

@@ -399,7 +400,7 @@ begin
 	end process;

 	

 	-- Address generation

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	variable slv_line : std_logic_vector(4 downto 0);

 	begin

 		if nRESET = '0' then

@@ -423,7 +424,7 @@ begin
 	end process;

 	

 	-- Cursor control

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	variable cursor_line : std_logic;

 	begin	

 		-- Internal cursor enable signal delayed by 1 clock to line up

@@ -459,7 +460,7 @@ begin
 	end process;

 	

 	-- Light pen capture

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin

 		if nRESET = '0' then

 			lpstb_i <= '0';

diff --git a/quartus/saa5050.vhd b/quartus/saa5050.vhd
index 57dd999..5fa1b2c 100644
--- a/quartus/saa5050.vhd
+++ b/quartus/saa5050.vhd
@@ -85,6 +85,7 @@ port (
 	);

 end entity;

 

+-- altera message_off 10036

 architecture rtl of saa5050 is

 

 component saa5050_rom IS

@@ -155,7 +156,7 @@ begin
 	flash <= flash_counter(5) and flash_counter(4);

 		

 	-- Sync inputs

-	process(DI_CLOCK,nRESET)

+	process(DI_CLOCK,nRESET,DI_CLKEN)

 	begin

 		if nRESET = '0' then

 			di_r <= (others => '0');

@@ -169,7 +170,7 @@ begin
 	end process;

 	

 	-- Register data into pixel clock domain

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin

 		if nRESET = '0' then

 			code <= (others => '0');

@@ -188,7 +189,7 @@ begin
 			gfx & code & std_logic_vector(line_addr);

 	

 	-- Character row and pixel counters

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin	

 		if nRESET = '0' then

 			dew_latch <= '0';

@@ -260,7 +261,7 @@ begin
 	end process;

 	

 	-- Shift register

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin

 		if nRESET = '0' then

 			shift_reg <= (others => '0');

@@ -292,7 +293,7 @@ begin
 	end process;

 	

 	-- Control character handling

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin	

 		if nRESET = '0' then

 			fg <= (others => '1');

@@ -363,7 +364,7 @@ begin
 	end process;

 	

 	-- Output

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN,shift_reg,flash,conceal,is_flash)

 	variable pixel : std_logic;

 	begin	

 		pixel := shift_reg(5) and not ((flash and is_flash) or conceal);

diff --git a/quartus/sn76489-1.0/sn76489_top.vhd b/quartus/sn76489-1.0/sn76489_top.vhd
index 277f601..f87cbb0 100644
--- a/quartus/sn76489-1.0/sn76489_top.vhd
+++ b/quartus/sn76489-1.0/sn76489_top.vhd
@@ -198,7 +198,7 @@ begin
 
 

 	-- Register output
-	process(clock_i)

+	process(clock_i,res_n_i)

 	begin

 		if res_n_i = '0' then

 			aout_o <= (others => '0');

diff --git a/quartus/vidproc.vhd b/quartus/vidproc.vhd
index 6d5f91f..25db750 100644
--- a/quartus/vidproc.vhd
+++ b/quartus/vidproc.vhd
@@ -165,7 +165,7 @@ begin
 	clken_fetch <= CLKEN and not (clken_counter(0) or clken_counter(1) or clken_counter(2) or

 		(clken_counter(3) and not r0_crtc_2mhz));

 		

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	begin

 		if nRESET = '0' then

 			clken_counter <= (others => '0');

@@ -176,7 +176,7 @@ begin
 	end process;

 	

 	-- Fetch control

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,clken_pixel)

 	begin

 		if nRESET = '0' then

 			shiftreg <= (others => '0');

@@ -197,7 +197,7 @@ begin
 		((r0_cursor0 and not (cursor_counter(0) or cursor_counter(1))) or

 		(r0_cursor1 and cursor_counter(0) and not cursor_counter(1)) or

 		(r0_cursor2 and cursor_counter(1)));

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,clken_fetch)

 	begin

 		if nRESET = '0' then

 			cursor_active <= '0';

@@ -231,7 +231,7 @@ begin
 	-- the pixel rate we ensure that the resulting delay is minimal and

 	-- constant (running this at the pixel rate would cause

 	-- the display to move slightly depending on which mode was selected). 

-	process(CLOCK,nRESET)

+	process(CLOCK,nRESET,CLKEN)

 	variable palette_a : std_logic_vector(3 downto 0);

 	variable dot_val : std_logic_vector(3 downto 0);

 	variable red_val : std_logic;