diff options
Diffstat (limited to 'roms/u-boot/board/freescale/p2020ds')
| -rw-r--r-- | roms/u-boot/board/freescale/p2020ds/Makefile | 12 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/p2020ds/ddr.c | 129 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/p2020ds/law.c | 20 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/p2020ds/p2020ds.c | 255 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/p2020ds/tlb.c | 90 |
5 files changed, 506 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/p2020ds/Makefile b/roms/u-boot/board/freescale/p2020ds/Makefile new file mode 100644 index 00000000..ee00806d --- /dev/null +++ b/roms/u-boot/board/freescale/p2020ds/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p2020ds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/roms/u-boot/board/freescale/p2020ds/ddr.c b/roms/u-boot/board/freescale/p2020ds/ddr.c new file mode 100644 index 00000000..debe70b1 --- /dev/null +++ b/roms/u-boot/board/freescale/p2020ds/ddr.c @@ -0,0 +1,129 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> + +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + * + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +static const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ +#ifdef CONFIG_SYS_FSL_DDR2 + {2, 549, 4, 0x1f, 2, 0}, + {2, 680, 4, 0x1f, 3, 0}, + {2, 850, 4, 0x1f, 4, 0}, + {1, 549, 4, 0x1f, 2, 0}, + {1, 680, 4, 0x1f, 3, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#else + {2, 850, 6, 0x1f, 4, 0}, + {1, 850, 4, 0x1f, 4, 0}, +#endif + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + int i; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + pbsp = dimm0; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } + +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + popts->wrlvl_en = 1; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x8; + /* Rtt and Rtt_WR override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_120_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ +} diff --git a/roms/u-boot/board/freescale/p2020ds/law.c b/roms/u-boot/board/freescale/p2020ds/law.c new file mode 100644 index 00000000..9cd4da97 --- /dev/null +++ b/roms/u-boot/board/freescale/p2020ds/law.c @@ -0,0 +1,20 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/roms/u-boot/board/freescale/p2020ds/p2020ds.c b/roms/u-boot/board/freescale/p2020ds/p2020ds.c new file mode 100644 index 00000000..a0cf9270 --- /dev/null +++ b/roms/u-boot/board/freescale/p2020ds/p2020ds.c @@ -0,0 +1,255 @@ +/* + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <fsl_ddr_sdram.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <netdev.h> + +#include "../common/ngpixis.h" +#include "../common/sgmii_riser.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ +#ifdef CONFIG_MMC + ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); +#endif + + return 0; +} + +int checkboard(void) +{ + u8 sw; + + printf("Board: P2020DS Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + /* The lower two bits are the actual vbank number */ + printf("vBank: %d\n", sw & 3); + else + puts("Promjet\n"); + + return 0; +} + +#if !defined(CONFIG_DDR_SPD) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + uint d_init; + + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; + ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; + ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; + ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; + ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; + ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; + + if (!strcmp("performance", getenv("perf_mode"))) { + /* Performance Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; + } else { + /* Stable Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + + /* ECC will be assumed in stable mode */ + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; + ddr->err_sbe = CONFIG_SYS_DDR_SBE; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) + udelay(1000); + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; +} + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_init(tsec_info, num); +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + + FT_FSL_PCI_SETUP; + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif +} +#endif diff --git a/roms/u-boot/board/freescale/p2020ds/tlb.c b/roms/u-boot/board/freescale/p2020ds/tlb.c new file mode 100644 index 00000000..02da6e8c --- /dev/null +++ b/roms/u-boot/board/freescale/p2020ds/tlb.c @@ -0,0 +1,90 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |