diff options
Diffstat (limited to 'roms/u-boot/board/freescale/mpc837xerdb')
| -rw-r--r-- | roms/u-boot/board/freescale/mpc837xerdb/Makefile | 9 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/mpc837xerdb/README | 97 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c | 211 | ||||
| -rw-r--r-- | roms/u-boot/board/freescale/mpc837xerdb/pci.c | 108 |
4 files changed, 425 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/mpc837xerdb/Makefile b/roms/u-boot/board/freescale/mpc837xerdb/Makefile new file mode 100644 index 00000000..c2d0bc43 --- /dev/null +++ b/roms/u-boot/board/freescale/mpc837xerdb/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mpc837xerdb.o +obj-$(CONFIG_PCI) += pci.o diff --git a/roms/u-boot/board/freescale/mpc837xerdb/README b/roms/u-boot/board/freescale/mpc837xerdb/README new file mode 100644 index 00000000..cfb6efa2 --- /dev/null +++ b/roms/u-boot/board/freescale/mpc837xerdb/README @@ -0,0 +1,97 @@ +Freescale MPC837xE-RDB Board +----------------------------------------- + +1. Board Description + + The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E, + MPC8378E, and the MPC8379E processors in a Mini-ITX form factor. + + The MPC837xE-RDB's have the following common features: + + A) 256-MBytes on-board DDR2 unbuffered SDRAM + B) 8-Mbytes NOR Flash + C) 32-MBytes NAND Flash + D) 1 Secure Digital High Speed Card (SDHC) Interface + E) 1 Gigabit Ethernet + F) 5-port Ethernet switch (Vitesse 7385) + G) 1 32-bit, 3.3 V, PCI slot + H) 1 32-bit, 3.3 V, Mini-PCI slot + I) 4-port USB 2.0 Hub + J) 1-port OTG USB + K) 2 serial ports (top main console) + L) on board Oscillator: 66M + + The MPC837xE-RDB's have the following differences: + + MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB + SATA controllers 2 0 4 + PCI-Express (mini) 2 2 0 + SGMII Ports 0 2 0 + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + Address Range Device Size Port Size + (Bytes) (Bits) + =========================== ================= ======= ========= + 0x0000_0000 0x0fff_ffff DDR 256M 64 + 0x1000_0000 0x7fff_ffff Empty 1.75G - + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32 + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32 + 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32 + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - + 0xe060_0000 0xe060_7fff NAND Flash 32K 8 + 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16 + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XERDB.h + + CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC837x MPC837x specific + CONFIG_MPC837XERDB MPC837xE-RDB board specific + + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XERDB_config + make + + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb $loadaddr + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp $loadaddr u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp $loadaddr u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b $loadaddr fe000000 $filesize + + +6. Additional Notes: + 1) The console is connected to the top RS-232 connector and the + baudrate for MPC837XE-RDB is 115200bps. diff --git a/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c b/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c new file mode 100644 index 00000000..9afdcaf7 --- /dev/null +++ b/roms/u-boot/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Kevin Lam <kevin.lam@freescale.com> + * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> +#include <fdt_support.h> +#include <spd_sdram.h> +#include <vsc7385.h> +#include <fsl_esdhc.h> + +#if defined(CONFIG_SYS_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize DDR ECC byte */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + /* return total bus DDR size(bytes) */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + sync(); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); + return CONFIG_SYS_DDR_SIZE; +} +#endif /*!CONFIG_SYS_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC837xERDB\n"); + return 0; +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (PARTID_NO_E(spridr)) { + case SPR_8377: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378: + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8379: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + + if (!hwconfig("esdhc")) + return 0; + + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); + + return fsl_esdhc_mmc_init(bd); +} +#endif + +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) + +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/roms/u-boot/board/freescale/mpc837xerdb/pci.c b/roms/u-boot/board/freescale/mpc837xerdb/pci.c new file mode 100644 index 00000000..8f50c936 --- /dev/null +++ b/roms/u-boot/board/freescale/mpc837xerdb/pci.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc83xx.h> +#include <pci.h> +#include <asm/io.h> + +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* Enable all 5 PCI_CLK_OUTPUTS */ + clk->occr |= 0xf8000000; + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg); + + /* There is no PEX in MPC8379 parts. */ + if (PARTID_NO_E(spridr) == SPR_8379) + return; + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +} |