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-rw-r--r--roms/u-boot/board/avnet/v5fx30teval/Makefile11
-rw-r--r--roms/u-boot/board/avnet/v5fx30teval/v5fx30teval.c17
-rw-r--r--roms/u-boot/board/avnet/v5fx30teval/xparameters.h22
3 files changed, 50 insertions, 0 deletions
diff --git a/roms/u-boot/board/avnet/v5fx30teval/Makefile b/roms/u-boot/board/avnet/v5fx30teval/Makefile
new file mode 100644
index 00000000..8c41af02
--- /dev/null
+++ b/roms/u-boot/board/avnet/v5fx30teval/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += v5fx30teval.o
+
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/roms/u-boot/board/avnet/v5fx30teval/v5fx30teval.c b/roms/u-boot/board/avnet/v5fx30teval/v5fx30teval.c
new file mode 100644
index 00000000..68b0eb95
--- /dev/null
+++ b/roms/u-boot/board/avnet/v5fx30teval/v5fx30teval.c
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+ puts("Avnet Virtex 5 FX30 Evaluation Board\n");
+ return 0;
+}
diff --git a/roms/u-boot/board/avnet/v5fx30teval/xparameters.h b/roms/u-boot/board/avnet/v5fx30teval/xparameters.h
new file mode 100644
index 00000000..95b8c285
--- /dev/null
+++ b/roms/u-boot/board/avnet/v5fx30teval/xparameters.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters.h by Xilinx
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+
+#endif