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-rw-r--r--roms/u-boot/board/LaCie/common/common.c105
-rw-r--r--roms/u-boot/board/LaCie/common/common.h18
-rw-r--r--roms/u-boot/board/LaCie/common/cpld-gpio-bus.c47
-rw-r--r--roms/u-boot/board/LaCie/common/cpld-gpio-bus.h21
4 files changed, 191 insertions, 0 deletions
diff --git a/roms/u-boot/board/LaCie/common/common.c b/roms/u-boot/board/LaCie/common/common.c
new file mode 100644
index 00000000..d6ffefec
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/common.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+
+#define MII_MARVELL_PHY_PAGE 22
+
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
+{
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /*
+ * Set control mode 4 for LED[0].
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+ miiphy_read(name, phyaddr, 16, &reg);
+ reg |= 0xf;
+ miiphy_write(name, phyaddr, 16, reg);
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1318 Initialized on %s\n", name);
+}
+#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac_addr)
+{
+ int ret;
+ ushort version;
+
+ /* I2C-0 for on-board EEPROM */
+ i2c_set_bus_num(0);
+
+ /* Check layout version for EEPROM data */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *) &version, 2);
+ if (ret != 0) {
+ printf("Error: failed to read I2C EEPROM @%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return ret;
+ }
+ version = be16_to_cpu(version);
+ if (version < 1 || version > 3) {
+ printf("Error: unknown version %d for EEPROM data\n",
+ version);
+ return -1;
+ }
+
+ /* Read Ethernet MAC address from EEPROM */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
+ if (ret != 0)
+ printf("Error: failed to read I2C EEPROM @%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return ret;
+}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
diff --git a/roms/u-boot/board/LaCie/common/common.h b/roms/u-boot/board/LaCie/common/common.h
new file mode 100644
index 00000000..c24e5885
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LACIE_COMMON_H
+#define _LACIE_COMMON_H
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
+#endif
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac);
+#endif
+
+#endif /* _LACIE_COMMON_H */
diff --git a/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644
index 00000000..9b24dc53
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c
@@ -0,0 +1,47 @@
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_addr; pin++)
+ kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_data; pin++)
+ kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+ /* The transfer is enabled on the raising edge. */
+ kw_gpio_set_value(bus->enable, 0);
+ kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+ unsigned addr, unsigned value)
+{
+ cpld_gpio_bus_set_addr(bus, addr);
+ cpld_gpio_bus_set_data(bus, value);
+ cpld_gpio_bus_enable_select(bus);
+}
diff --git a/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644
index 00000000..3dfac0b5
--- /dev/null
+++ b/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+ unsigned *addr;
+ unsigned num_addr;
+ unsigned *data;
+ unsigned num_data;
+ unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+ unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-04 00:55:18 +0000