diff options
Diffstat (limited to 'roms/u-boot/arch/avr32/include/asm/arch-at32ap700x')
9 files changed, 636 insertions, 0 deletions
diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h new file mode 100644 index 00000000..7b25e2ef --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ADDRSPACE_H +#define __ASM_AVR32_ADDRSPACE_H + +#include <asm/types.h> + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +/* virt_to_phys will only work when address is in P1 or P2 */ +static inline unsigned long virt_to_phys(volatile void *address) +{ + return PHYSADDR(address); +} + +static inline void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define cached(addr) ((void *)P1SEGADDR(addr)) +#define uncached(addr) ((void *)P2SEGADDR(addr)) + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + * + * This implementation works for memory below 512MiB (flash, etc.) as + * well as above 3.5GiB (internal peripherals.) + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (1 << 7) +#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) +#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h new file mode 100644 index 00000000..13d6d3ae --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_CACHEFLUSH_H +#define __ASM_AVR32_CACHEFLUSH_H + +/* + * Invalidate any cacheline containing virtual address vaddr without + * writing anything back to memory. + * + * Note that this function may corrupt unrelated data structures when + * applied on buffers that are not cacheline aligned in both ends. + */ +static inline void dcache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory. + */ +static inline void dcache_clean_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory and then invalidate it. + */ +static inline void dcache_flush_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); +} + +/* + * Invalidate any instruction cacheline containing virtual address + * vaddr. + */ +static inline void icache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); +} + +/* + * Applies the above functions on all lines that are touched by the + * specified virtual address range. + */ +void dcache_invalidate_range(volatile void *start, size_t len); +void dcache_clean_range(volatile void *start, size_t len); +void dcache_flush_range(volatile void *start, size_t len); +void icache_invalidate_range(volatile void *start, size_t len); + +static inline void dcache_flush_unlocked(void) +{ + asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); +} + +/* + * Make sure any pending writes are completed before continuing. + */ +#define sync_write_buffer() asm volatile("sync 0" : : : "memory") + +#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h new file mode 100644 index 00000000..822286df --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ +#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ + +/* Currently, all the AP700x chips have these */ +#define AT32AP700x_CHIP_HAS_USART +#define AT32AP700x_CHIP_HAS_MMCI +#define AT32AP700x_CHIP_HAS_SPI + +/* Only AP7000 has ethernet interface */ +#ifdef CONFIG_AT32AP7000 +#define AT32AP700x_CHIP_HAS_MACB +#endif + +/* AP7000 and AP7002 have LCD controller, but AP7001 does not */ +#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002) +#define AT32AP700x_CHIP_HAS_LCDC +#endif + +#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h new file mode 100644 index 00000000..0721899f --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#include <asm/arch/chip-features.h> +#include <asm/arch/portmux.h> + +#ifdef CONFIG_PLL +#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \ + * CONFIG_SYS_PLL0_MUL) +#define MAIN_CLK_RATE PLL0_RATE +#else +#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +#ifdef AT32AP700x_CHIP_HAS_USART +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_SPI +static inline unsigned long get_spi_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_LCDC +static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +#endif + +extern void clk_init(void); + +/* Board code may need the SDRAM base clock as a compile-time constant */ +#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) + +/* Generic clock control */ +enum gclk_parent { + GCLK_PARENT_OSC0 = 0, + GCLK_PARENT_OSC1 = 1, + GCLK_PARENT_PLL0 = 2, + GCLK_PARENT_PLL1 = 3, +}; + +/* Some generic clocks have specific roles */ +#define GCLK_DAC_SAMPLE_CLK 6 +#define GCLK_LCDC_PIXCLK 7 + +extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, + unsigned long rate, unsigned long parent_rate); + +/** + * gclk_set_rate - configure and enable a generic clock + * @id: Which GCLK[id] to enable + * @parent: Parent clock feeding the GCLK + * @rate: Target rate of the GCLK in Hz + * + * Returns the actual GCLK rate in Hz, after rounding to the nearest + * supported rate. + * + * All three parameters are usually constant, hence the inline. + */ +static inline unsigned long gclk_set_rate(unsigned int id, + enum gclk_parent parent, unsigned long rate) +{ + unsigned long parent_rate; + + if (id > 7) + return 0; + + switch (parent) { + case GCLK_PARENT_OSC0: + parent_rate = CONFIG_SYS_OSC0_HZ; + break; +#ifdef CONFIG_SYS_OSC1_HZ + case GCLK_PARENT_OSC1: + parent_rate = CONFIG_SYS_OSC1_HZ; + break; +#endif +#ifdef PLL0_RATE + case GCLK_PARENT_PLL0: + parent_rate = PLL0_RATE; + break; +#endif +#ifdef PLL1_RATE + case GCLK_PARENT_PLL1: + parent_rate = PLL1_RATE; + break; +#endif + default: + parent_rate = 0; + break; + } + + return __gclk_set_rate(id, parent, rate, parent_rate); +} + +/** + * gclk_enable_output - enable output on a GCLK pin + * @id: Which GCLK[id] pin to enable + * @drive_strength: Drive strength of external GCLK pin, if applicable + */ +static inline void gclk_enable_output(unsigned int id, + unsigned long drive_strength) +{ + switch (id) { + case 0: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + case 1: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, + PORTMUX_FUNC_A, drive_strength); + break; + case 2: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, + PORTMUX_FUNC_A, drive_strength); + break; + case 3: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, + PORTMUX_FUNC_A, drive_strength); + break; + case 4: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + } +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h new file mode 100644 index 00000000..b5808c5d --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ARCH_GPIO_H__ +#define __ASM_AVR32_ARCH_GPIO_H__ + +#include <asm/arch/chip-features.h> +#include <asm/arch/hardware.h> + +#define NR_GPIO_CONTROLLERS 5 + +/* + * Pin numbers identifying specific GPIO pins on the chip. + */ +#define GPIO_PIOA_BASE (0) +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) +#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) +#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) +#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) +#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) + +static inline void *pio_pin_to_port(unsigned int pin) +{ + switch (pin >> 5) { + case 0: + return (void *)ATMEL_BASE_PIOA; + case 1: + return (void *)ATMEL_BASE_PIOB; + case 2: + return (void *)ATMEL_BASE_PIOC; + case 3: + return (void *)ATMEL_BASE_PIOD; + case 4: + return (void *)ATMEL_BASE_PIOE; + default: + return NULL; + } +} + +#include <asm/arch-common/portmux-pio.h> + +#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h new file mode 100644 index 00000000..58ae9652 --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __AT32AP7000_HARDWARE_H__ +#define __AT32AP7000_HARDWARE_H__ + +/* Internal and external memories */ +#define EBI_SRAM_CS0_BASE 0x00000000 +#define EBI_SRAM_CS0_SIZE 0x04000000 +#define EBI_SRAM_CS4_BASE 0x04000000 +#define EBI_SRAM_CS4_SIZE 0x04000000 +#define EBI_SRAM_CS2_BASE 0x08000000 +#define EBI_SRAM_CS2_SIZE 0x04000000 +#define EBI_SRAM_CS3_BASE 0x0c000000 +#define EBI_SRAM_CS3_SIZE 0x04000000 +#define EBI_SRAM_CS1_BASE 0x10000000 +#define EBI_SRAM_CS1_SIZE 0x10000000 +#define EBI_SRAM_CS5_BASE 0x20000000 +#define EBI_SRAM_CS5_SIZE 0x04000000 + +#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE +#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE + +#define INTERNAL_SRAM_BASE 0x24000000 +#define INTERNAL_SRAM_SIZE 0x00008000 + +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 + +/* Devices on Peripheral Bus A (PBA) */ +#define ATMEL_BASE_SPI0 0xFFE00000 +#define ATMEL_BASE_SPI1 0xFFE00400 +#define ATMEL_BASE_TWI0 0xFFE00800 +#define ATMEL_BASE_USART0 0xFFE00C00 +#define ATMEL_BASE_USART1 0xFFE01000 +#define ATMEL_BASE_USART2 0xFFE01400 +#define ATMEL_BASE_USART3 0xFFE01800 +#define ATMEL_BASE_SSC0 0xFFE01C00 +#define ATMEL_BASE_SSC1 0xFFE02000 +#define ATMEL_BASE_SSC2 0xFFE02400 +#define ATMEL_BASE_PIOA 0xFFE02800 +#define ATMEL_BASE_PIOB 0xFFE02C00 +#define ATMEL_BASE_PIOC 0xFFE03000 +#define ATMEL_BASE_PIOD 0xFFE03400 +#define ATMEL_BASE_PIOE 0xFFE03800 +#define ATMEL_BASE_PSIF 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define ATMEL_BASE_SM 0xFFF00000 +#define ATMEL_BASE_INTC 0xFFF00400 +#define ATMEL_BASE_HMATRIX 0xFFF00800 +#define ATMEL_BASE_TIMER0 0xFFF00C00 +#define ATMEL_BASE_TIMER1 0xFFF01000 +#define ATMEL_BASE_PWM 0xFFF01400 +#define ATMEL_BASE_MACB0 0xFFF01800 +#define ATMEL_BASE_MACB1 0xFFF01C00 +#define ATMEL_BASE_DAC 0xFFF02000 +#define ATMEL_BASE_MMCI 0xFFF02400 +#define ATMEL_BASE_AUDIOC 0xFFF02800 +#define ATMEL_BASE_HISI 0xFFF02C00 +#define ATMEL_BASE_USB 0xFFF03000 +#define ATMEL_BASE_HSMC 0xFFF03400 +#define ATMEL_BASE_HSDRAMC 0xFFF03800 +#define ATMEL_BASE_ECC 0xFFF03C00 + +#endif /* __AT32AP7000_HARDWARE_H__ */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h new file mode 100644 index 00000000..d2a733fa --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ +#define __ASM_AVR32_ARCH_HMATRIX_H__ + +#include <asm/hmatrix-common.h> + +/* Bitfields in SFR4 (EBI) */ +#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 +#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 +#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 +#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 +#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 +#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 +#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 +#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 +#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 +#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 + +/* HSB masters */ +#define HMATRIX_MASTER_CPU_DCACHE 0 +#define HMATRIX_MASTER_CPU_ICACHE 1 +#define HMATRIX_MASTER_PDC 2 +#define HMATRIX_MASTER_ISI 3 +#define HMATRIX_MASTER_USBA 4 +#define HMATRIX_MASTER_LCDC 5 +#define HMATRIX_MASTER_MACB0 6 +#define HMATRIX_MASTER_MACB1 7 +#define HMATRIX_MASTER_DMACA_M0 8 +#define HMATRIX_MASTER_DMACA_M1 9 + +/* HSB slaves */ +#define HMATRIX_SLAVE_SRAM0 0 +#define HMATRIX_SLAVE_SRAM1 1 +#define HMATRIX_SLAVE_PBA 2 +#define HMATRIX_SLAVE_PBB 3 +#define HMATRIX_SLAVE_EBI 4 +#define HMATRIX_SLAVE_USBA 5 +#define HMATRIX_SLAVE_LCDC 6 +#define HMATRIX_SLAVE_DMACA 7 + +#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h new file mode 100644 index 00000000..fcd9a056 --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h @@ -0,0 +1,66 @@ +/* + * In order to deal with the hardcoded u-boot requirement that virtual + * addresses are always mapped 1:1 with physical addresses, we implement + * a small virtual memory manager so that we can use the MMU hardware in + * order to get the caching properties right. + * + * A few pages (or possibly just one) are locked in the TLB permanently + * in order to avoid recursive TLB misses, but most pages are faulted in + * on demand. + */ +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +#include <asm/sysreg.h> + +#define PAGE_SHIFT 20 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1)) + +#define MMU_VMR_CACHE_NONE \ + (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) +#define MMU_VMR_CACHE_WBUF \ + (MMU_VMR_CACHE_NONE | SYSREG_BIT(B)) +#define MMU_VMR_CACHE_WRTHRU \ + (MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W)) +#define MMU_VMR_CACHE_WRBACK \ + (MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C)) + +/* + * This structure is used in our "page table". Instead of the usual + * x86-inspired radix tree, we let each entry cover an arbitrary-sized + * virtual address range and store them in a binary search tree. This is + * somewhat slower, but should use significantly less RAM, and we + * shouldn't get many TLB misses when using 1 MB pages anyway. + * + * With 1 MB pages, we need 12 bits to store the page number. In + * addition, we stick an Invalid bit in the high bit of virt_pgno (if + * set, it cannot possibly match any faulting page), and all the bits + * that need to be written to TLBELO in phys_pgno. + */ +struct mmu_vm_range { + uint16_t virt_pgno; + uint16_t nr_pages; + uint32_t phys; +}; + +/* + * An array of mmu_vm_range objects describing all pageable addresses. + * The array is sorted by virt_pgno so that the TLB miss exception + * handler can do a binary search to find the correct entry. + */ +extern struct mmu_vm_range mmu_vmr_table[]; + +/* + * Initialize the MMU. This will set up a fixed TLB entry for the static + * u-boot image at dest_addr and enable paging. + */ +void mmu_init_r(unsigned long dest_addr); + +/* + * Handle a TLB miss exception. This function is called directly from + * the exception vector table written in assembly. + */ +int mmu_handle_tlb_miss(void); + +#endif /* __ASM_ARCH_MMU_H */ diff --git a/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h new file mode 100644 index 00000000..7ae05408 --- /dev/null +++ b/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_AVR32_ARCH_PORTMUX_H__ +#define __ASM_AVR32_ARCH_PORTMUX_H__ + +#include <asm/arch/gpio.h> + +#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA) +#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB) +#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC) +#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD) +#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE) + +void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, + unsigned long flags, unsigned long drive_strength); + +#define PORTMUX_EBI_CS(x) (1 << (x)) +#define PORTMUX_EBI_NAND (1 << 6) +#define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) +#define PORTMUX_EBI_NWAIT (1 << 9) + +#ifdef AT32AP700x_CHIP_HAS_USART +static inline void portmux_enable_usart0(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), + PORTMUX_FUNC_B, 0); +} + +static inline void portmux_enable_usart1(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), + PORTMUX_FUNC_A, 0); +} + +static inline void portmux_enable_usart2(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), + PORTMUX_FUNC_B, 0); +} + +static inline void portmux_enable_usart3(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), + PORTMUX_FUNC_B, 0); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB +void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); +void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); + +#define PORTMUX_MACB_RMII (0) +#define PORTMUX_MACB_MII (1 << 0) +#define PORTMUX_MACB_SPEED (1 << 1) + +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI +void portmux_enable_mmci(unsigned int slot, unsigned long flags, + unsigned long drive_strength); + +#define PORTMUX_MMCI_4BIT (1 << 0) +#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) +#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) + +#endif +#ifdef AT32AP700x_CHIP_HAS_SPI +void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); +void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); +#endif +#ifdef AT32AP700x_CHIP_HAS_LCDC +void portmux_enable_lcdc(int pin_config); +#endif + +#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ |