diff options
Diffstat (limited to 'roms/u-boot/arch/arm/include/asm/arch-s3c24x0')
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h | 155 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h | 184 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h | 159 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h | 136 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h | 147 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 145 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 704 | ||||
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h | 16 |
8 files changed, 1646 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644 index 00000000..a749b649 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2012. + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _S3C24X0_GPIO_H_ +#define _S3C24X0_GPIO_H_ + +enum s3c2440_gpio { + GPA0, + GPA1, + GPA2, + GPA3, + GPA4, + GPA5, + GPA6, + GPA7, + GPA8, + GPA9, + GPA10, + GPA11, + GPA12, + GPA13, + GPA14, + GPA15, + GPA16, + GPA17, + GPA18, + GPA19, + GPA20, + GPA21, + GPA22, + GPA23, + GPA24, + + GPB0 = 32, + GPB1, + GPB2, + GPB3, + GPB4, + GPB5, + GPB6, + GPB7, + GPB8, + GPB9, + GPB10, + + GPC0 = 64, + GPC1, + GPC2, + GPC3, + GPC4, + GPC5, + GPC6, + GPC7, + GPC8, + GPC9, + GPC10, + GPC11, + GPC12, + GPC13, + GPC14, + GPC15, + + GPD0 = 96, + GPD1, + GPD2, + GPD3, + GPD4, + GPD5, + GPD6, + GPD7, + GPD8, + GPD9, + GPD10, + GPD11, + GPD12, + GPD13, + GPD14, + GPD15, + + GPE0 = 128, + GPE1, + GPE2, + GPE3, + GPE4, + GPE5, + GPE6, + GPE7, + GPE8, + GPE9, + GPE10, + GPE11, + GPE12, + GPE13, + GPE14, + GPE15, + + GPF0 = 160, + GPF1, + GPF2, + GPF3, + GPF4, + GPF5, + GPF6, + GPF7, + + GPG0 = 192, + GPG1, + GPG2, + GPG3, + GPG4, + GPG5, + GPG6, + GPG7, + GPG8, + GPG9, + GPG10, + GPG11, + GPG12, + GPG13, + GPG14, + GPG15, + + GPH0 = 224, + GPH1, + GPH2, + GPH3, + GPH4, + GPH5, + GPH6, + GPH7, + GPH8, + GPH9, + GPH10, + + GPJ0 = 256, + GPJ1, + GPJ2, + GPJ3, + GPJ4, + GPJ5, + GPJ6, + GPJ7, + GPJ8, + GPJ9, + GPJ10, + GPJ11, + GPJ12, +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644 index 00000000..98116443 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2012 + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _S3C24X0_IOMUX_H_ +#define _S3C24X0_IOMUX_H_ + +enum s3c2440_iomux_func { + /* PORT A */ + IOMUXA_ADDR0 = 1, + IOMUXA_ADDR16 = (1 << 1), + IOMUXA_ADDR17 = (1 << 2), + IOMUXA_ADDR18 = (1 << 3), + IOMUXA_ADDR19 = (1 << 4), + IOMUXA_ADDR20 = (1 << 5), + IOMUXA_ADDR21 = (1 << 6), + IOMUXA_ADDR22 = (1 << 7), + IOMUXA_ADDR23 = (1 << 8), + IOMUXA_ADDR24 = (1 << 9), + IOMUXA_ADDR25 = (1 << 10), + IOMUXA_ADDR26 = (1 << 11), + IOMUXA_nGCS1 = (1 << 12), + IOMUXA_nGCS2 = (1 << 13), + IOMUXA_nGCS3 = (1 << 14), + IOMUXA_nGCS4 = (1 << 15), + IOMUXA_nGCS5 = (1 << 16), + IOMUXA_CLE = (1 << 17), + IOMUXA_ALE = (1 << 18), + IOMUXA_nFWE = (1 << 19), + IOMUXA_nFRE = (1 << 20), + IOMUXA_nRSTOUT = (1 << 21), + IOMUXA_nFCE = (1 << 22), + + /* PORT B */ + IOMUXB_nXDREQ0 = (2 << 20), + IOMUXB_nXDACK0 = (2 << 18), + IOMUXB_nXDREQ1 = (2 << 16), + IOMUXB_nXDACK1 = (2 << 14), + IOMUXB_nXBREQ = (2 << 12), + IOMUXB_nXBACK = (2 << 10), + IOMUXB_TCLK0 = (2 << 8), + IOMUXB_TOUT3 = (2 << 6), + IOMUXB_TOUT2 = (2 << 4), + IOMUXB_TOUT1 = (2 << 2), + IOMUXB_TOUT0 = 2, + + /* PORT C */ + IOMUXC_VS7 = (2 << 30), + IOMUXC_VS6 = (2 << 28), + IOMUXC_VS5 = (2 << 26), + IOMUXC_VS4 = (2 << 24), + IOMUXC_VS3 = (2 << 22), + IOMUXC_VS2 = (2 << 20), + IOMUXC_VS1 = (2 << 18), + IOMUXC_VS0 = (2 << 16), + IOMUXC_LCD_LPCREVB = (2 << 14), + IOMUXC_LCD_LPCREV = (2 << 12), + IOMUXC_LCD_LPCOE = (2 << 10), + IOMUXC_VM = (2 << 8), + IOMUXC_VFRAME = (2 << 6), + IOMUXC_VLINE = (2 << 4), + IOMUXC_VCLK = (2 << 2), + IOMUXC_LEND = 2, + IOMUXC_I2SSDI = (3 << 8), + + /* PORT D */ + IOMUXD_VS23 = (2 << 30), + IOMUXD_VS22 = (2 << 28), + IOMUXD_VS21 = (2 << 26), + IOMUXD_VS20 = (2 << 24), + IOMUXD_VS19 = (2 << 22), + IOMUXD_VS18 = (2 << 20), + IOMUXD_VS17 = (2 << 18), + IOMUXD_VS16 = (2 << 16), + IOMUXD_VS15 = (2 << 14), + IOMUXD_VS14 = (2 << 12), + IOMUXD_VS13 = (2 << 10), + IOMUXD_VS12 = (2 << 8), + IOMUXD_VS11 = (2 << 6), + IOMUXD_VS10 = (2 << 4), + IOMUXD_VS9 = (2 << 2), + IOMUXD_VS8 = 2, + IOMUXD_nSS0 = (3 << 30), + IOMUXD_nSS1 = (3 << 28), + IOMUXD_SPICLK1 = (3 << 20), + IOMUXD_SPIMOSI1 = (3 << 18), + IOMUXD_SPIMISO1 = (3 << 16), + + /* PORT E */ + IOMUXE_IICSDA = (2 << 30), + IOMUXE_IICSCL = (2 << 28), + IOMUXE_SPICLK0 = (2 << 26), + IOMUXE_SPIMOSI0 = (2 << 24), + IOMUXE_SPIMISO0 = (2 << 22), + IOMUXE_SDDAT3 = (2 << 20), + IOMUXE_SDDAT2 = (2 << 18), + IOMUXE_SDDAT1 = (2 << 16), + IOMUXE_SDDAT0 = (2 << 14), + IOMUXE_SDCMD = (2 << 12), + IOMUXE_SDCLK = (2 << 10), + IOMUXE_I2SDO = (2 << 8), + IOMUXE_I2SDI = (2 << 6), + IOMUXE_CDCLK = (2 << 4), + IOMUXE_I2SSCLK = (2 << 2), + IOMUXE_I2SLRCK = 2, + IOMUXE_AC_SDATA_OUT = (3 << 8), + IOMUXE_AC_SDATA_IN = (3 << 6), + IOMUXE_AC_nRESET = (3 << 4), + IOMUXE_AC_BIT_CLK = (3 << 2), + IOMUXE_AC_SYNC = 3, + + /* PORT F */ + IOMUXF_EINT7 = (2 << 14), + IOMUXF_EINT6 = (2 << 12), + IOMUXF_EINT5 = (2 << 10), + IOMUXF_EINT4 = (2 << 8), + IOMUXF_EINT3 = (2 << 6), + IOMUXF_EINT2 = (2 << 4), + IOMUXF_EINT1 = (2 << 2), + IOMUXF_EINT0 = 2, + + /* PORT G */ + IOMUXG_EINT23 = (2 << 30), + IOMUXG_EINT22 = (2 << 28), + IOMUXG_EINT21 = (2 << 26), + IOMUXG_EINT20 = (2 << 24), + IOMUXG_EINT19 = (2 << 22), + IOMUXG_EINT18 = (2 << 20), + IOMUXG_EINT17 = (2 << 18), + IOMUXG_EINT16 = (2 << 16), + IOMUXG_EINT15 = (2 << 14), + IOMUXG_EINT14 = (2 << 12), + IOMUXG_EINT13 = (2 << 10), + IOMUXG_EINT12 = (2 << 8), + IOMUXG_EINT11 = (2 << 6), + IOMUXG_EINT10 = (2 << 4), + IOMUXG_EINT9 = (2 << 2), + IOMUXG_EINT8 = 2, + IOMUXG_TCLK1 = (3 << 22), + IOMUXG_nCTS1 = (3 << 20), + IOMUXG_nRTS1 = (3 << 18), + IOMUXG_SPICLK1 = (3 << 14), + IOMUXG_SPIMOSI1 = (3 << 12), + IOMUXG_SPIMISO1 = (3 << 10), + IOMUXG_LCD_PWRDN = (3 << 8), + IOMUXG_nSS1 = (3 << 6), + IOMUXG_nSS0 = (3 << 4), + + /* PORT H */ + IOMUXH_CLKOUT1 = (2 << 20), + IOMUXH_CLKOUT0 = (2 << 18), + IOMUXH_UEXTCLK = (2 << 16), + IOMUXH_RXD2 = (2 << 14), + IOMUXH_TXD2 = (2 << 12), + IOMUXH_RXD1 = (2 << 10), + IOMUXH_TXD1 = (2 << 8), + IOMUXH_RXD0 = (2 << 6), + IOMUXH_TXD0 = (2 << 4), + IOMUXH_nRTS0 = (2 << 2), + IOMUXH_nCTS0 = 2, + IOMUXH_nCTS1 = (3 << 14), + IOMUXH_nRTS1 = (3 << 12), + + /* PORT J */ + IOMUXJ_CAMRESET = (2 << 24), + IOMUXJ_CAMCLKOUT = (2 << 22), + IOMUXJ_CAMHREF = (2 << 20), + IOMUXJ_CAMVSYNC = (2 << 18), + IOMUXJ_CAMPCLK = (2 << 16), + IOMUXJ_CAMDATA7 = (2 << 14), + IOMUXJ_CAMDATA6 = (2 << 12), + IOMUXJ_CAMDATA5 = (2 << 10), + IOMUXJ_CAMDATA4 = (2 << 8), + IOMUXJ_CAMDATA3 = (2 << 6), + IOMUXJ_CAMDATA2 = (2 << 4), + IOMUXJ_CAMDATA1 = (2 << 2), + IOMUXJ_CAMDATA0 = 2 +}; + +#endif diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h new file mode 100644 index 00000000..d6a787b6 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h @@ -0,0 +1,159 @@ +/* + * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de + * based on + * linux/include/asm-arm/arch-sa1100/memory.h + * + * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com> + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset is 0x0c000000 on the S3C2400 + */ +#define PHYS_OFFSET (0x0c000000UL) + +/* Modified for S3C2400, by chc, 20010509 */ +#define RAM_IN_BANK_0 32*1024*1024 +#define RAM_IN_BANK_1 0 +#define RAM_IN_BANK_2 0 +#define RAM_IN_BANK_3 0 + +#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) + + +/* translation macros */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro + +#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) + +#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) +#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) + +#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ + (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) + +/* Two identical banks */ +#define __virt_to_phys(x) \ + ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ + ((x) - PAGE_OFFSET + _DRAMBnk0) : \ + ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) +#define __phys_to_virt(x) \ + ( ((x)&0x07ffffff) + \ + (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) +#else + +/* It's more efficient for all other cases to use the function call */ +#undef __virt_to_phys__is_a_macro +#undef __phys_to_virt__is_a_macro +extern unsigned long __virt_to_phys(unsigned long vpage); +extern unsigned long __phys_to_virt(unsigned long ppage); + +#endif + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + * + * On the SA1100, bus addresses are equivalent to physical addresses. + */ +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) __phys_to_virt(x) + + +#ifdef CONFIG_DISCONTIGMEM +#error "CONFIG_DISCONTIGMEM will not work on S3C2400" +/* + * Because of the wide memory address space between physical RAM banks on the + * SA1100, it's much more convenient to use Linux's NUMA support to implement + * our memory map representation. Assuming all memory nodes have equal access + * characteristics, we then have generic discontiguous memory support. + * + * Of course, all this isn't mandatory for SA1100 implementations with only + * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. + * + * The nodes are matched with the physical memory bank addresses which are + * incidentally the same as virtual addresses. + * + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff + */ + +#define NR_NODES 4 + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) \ + (((unsigned long)(addr) - 0xc0000000) >> 27) + +/* + * Given a physical address, convert it to a node id. + */ +#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) \ + NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(kvaddr) \ + (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) + +/* + * Given a kaddr, virt_to_page returns a pointer to the corresponding + * mem_map entry. + */ +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +/* + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they refer to. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ( (node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ +}) + +#else + +#define PHYS_TO_NID(addr) (0) + +#endif +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h new file mode 100644 index 00000000..2389118e --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************ + * NAME : s3c2400.h + * Version : 31.3.2003 + * + * Based on S3C2400X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2400_H__ +#define __S3C2400_H__ + +#define S3C24X0_UART_CHANNELS 2 +#define S3C24X0_SPI_CHANNELS 1 +#define PALETTE (0x14A00400) /* SJS */ + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, +}; + +/*S3C2400 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x14000000 +#define S3C24X0_USB_HOST_BASE 0x14200000 +#define S3C24X0_INTERRUPT_BASE 0x14400000 +#define S3C24X0_DMA_BASE 0x14600000 +#define S3C24X0_CLOCK_POWER_BASE 0x14800000 +#define S3C24X0_LCD_BASE 0x14A00000 +#define S3C24X0_UART_BASE 0x15000000 +#define S3C24X0_TIMER_BASE 0x15100000 +#define S3C24X0_USB_DEVICE_BASE 0x15200140 +#define S3C24X0_WATCHDOG_BASE 0x15300000 +#define S3C24X0_I2C_BASE 0x15400000 +#define S3C24X0_I2S_BASE 0x15508000 +#define S3C24X0_GPIO_BASE 0x15600000 +#define S3C24X0_RTC_BASE 0x15700000 +#define S3C24X0_ADC_BASE 0x15800000 +#define S3C24X0_SPI_BASE 0x15900000 +#define S3C2400_MMC_BASE 0x15A00000 + +/* include common stuff */ +#include <asm/arch/s3c24x0.h> + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} + +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} + +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} + +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} + +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} + +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} + +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} + +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} + +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} + +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} + +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} + +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} + +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} + +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} + +static inline struct s3c2400_adc *s3c2400_get_base_adc(void) +{ + return (struct s3c2400_adc *)S3C24X0_ADC_BASE; +} + +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} + +static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) +{ + return (struct s3c2400_mmc *)S3C2400_MMC_BASE; +} + +#endif /*__S3C2400_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h new file mode 100644 index 00000000..01fe0f27 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************ + * NAME : s3c2410.h + * Version : 31.3.2003 + * + * Based on S3C2410X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2410_H__ +#define __S3C2410_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2410 only supports 512 Byte HW ECC */ +#define S3C2410_ECCSIZE 512 +#define S3C2410_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2410 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2410_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include <asm/arch/s3c24x0.h> + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} + +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} + +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} + +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} + +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} + +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} + +static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +{ + return (struct s3c2410_nand *)S3C2410_NAND_BASE; +} + +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} + +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} + +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} + +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} + +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} + +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} + +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} + +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} + +static inline struct s3c2410_adc *s3c2410_get_base_adc(void) +{ + return (struct s3c2410_adc *)S3C2410_ADC_BASE; +} + +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} + +static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) +{ + return (struct s3c2410_sdi *)S3C2410_SDI_BASE; +} + +#endif /*__S3C2410_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h new file mode 100644 index 00000000..15a7cb43 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2003 + * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************ + * NAME : s3c2440.h + * Version : 31.3.2003 + * + * Based on S3C2440 User's manual Rev x.x + ************************************************/ + +#ifndef __S3C2440_H__ +#define __S3C2440_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2440 only supports 512 Byte HW ECC */ +#define S3C2440_ECCSIZE 512 +#define S3C2440_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2440 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2440_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2440_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2440_SDI_BASE 0x5A000000 + +/* include common stuff */ +#include <asm/arch/s3c24x0.h> + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} + +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} + +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} + +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} + +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} + +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} + +static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +{ + return (struct s3c2440_nand *)S3C2440_NAND_BASE; +} + +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} + +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} + +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} + +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} + +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} + +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} + +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} + +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} + +static inline struct s3c2440_adc *s3c2440_get_base_adc(void) +{ + return (struct s3c2440_adc *)S3C2440_ADC_BASE; +} + +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} + +static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +{ + return (struct s3c2440_sdi *)S3C2440_SDI_BASE; +} + +#endif /*__S3C2440_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h new file mode 100644 index 00000000..86d720c0 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -0,0 +1,704 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************ + * NAME : s3c24x0.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C24X0 SoC + ************************************************/ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +/* Memory controller (see manual chapter 5) */ +struct s3c24x0_memctl { + u32 bwscon; + u32 bankcon[8]; + u32 refresh; + u32 banksize; + u32 mrsrb6; + u32 mrsrb7; +}; + + +/* USB HOST (see manual chapter 12) */ +struct s3c24x0_usb_host { + u32 HcRevision; + u32 HcControl; + u32 HcCommonStatus; + u32 HcInterruptStatus; + u32 HcInterruptEnable; + u32 HcInterruptDisable; + u32 HcHCCA; + u32 HcPeriodCuttendED; + u32 HcControlHeadED; + u32 HcControlCurrentED; + u32 HcBulkHeadED; + u32 HcBuldCurrentED; + u32 HcDoneHead; + u32 HcRmInterval; + u32 HcFmRemaining; + u32 HcFmNumber; + u32 HcPeriodicStart; + u32 HcLSThreshold; + u32 HcRhDescriptorA; + u32 HcRhDescriptorB; + u32 HcRhStatus; + u32 HcRhPortStatus1; + u32 HcRhPortStatus2; +}; + + +/* INTERRUPT (see manual chapter 14) */ +struct s3c24x0_interrupt { + u32 srcpnd; + u32 intmod; + u32 intmsk; + u32 priority; + u32 intpnd; + u32 intoffset; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 subsrcpnd; + u32 intsubmsk; +#endif +}; + + +/* DMAS (see manual chapter 8) */ +struct s3c24x0_dma { + u32 disrc; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 disrcc; +#endif + u32 didst; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 didstc; +#endif + u32 dcon; + u32 dstat; + u32 dcsrc; + u32 dcdst; + u32 dmasktrig; +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ + || defined(CONFIG_S3C2440) + u32 res[1]; +#endif +}; + +struct s3c24x0_dmas { + struct s3c24x0_dma dma[4]; +}; + + +/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ +/* (see S3C2410 manual chapter 7) */ +struct s3c24x0_clock_power { + u32 locktime; + u32 mpllcon; + u32 upllcon; + u32 clkcon; + u32 clkslow; + u32 clkdivn; +#if defined(CONFIG_S3C2440) + u32 camdivn; +#endif +}; + + +/* LCD CONTROLLER (see manual chapter 15) */ +struct s3c24x0_lcd { + u32 lcdcon1; + u32 lcdcon2; + u32 lcdcon3; + u32 lcdcon4; + u32 lcdcon5; + u32 lcdsaddr1; + u32 lcdsaddr2; + u32 lcdsaddr3; + u32 redlut; + u32 greenlut; + u32 bluelut; + u32 res[8]; + u32 dithmode; + u32 tpal; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 lcdintpnd; + u32 lcdsrcpnd; + u32 lcdintmsk; + u32 lpcsel; +#endif +}; + + +#ifdef CONFIG_S3C2410 +/* NAND FLASH (see S3C2410 manual chapter 6) */ +struct s3c2410_nand { + u32 nfconf; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfstat; + u32 nfecc; +}; +#endif +#ifdef CONFIG_S3C2440 +/* NAND FLASH (see S3C2440 manual chapter 6) */ +struct s3c2440_nand { + u32 nfconf; + u32 nfcont; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfeccd0; + u32 nfeccd1; + u32 nfeccd; + u32 nfstat; + u32 nfstat0; + u32 nfstat1; +}; +#endif + + +/* UART (see manual chapter 11) */ +struct s3c24x0_uart { + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 utrstat; + u32 uerstat; + u32 ufstat; + u32 umstat; +#ifdef __BIG_ENDIAN + u8 res1[3]; + u8 utxh; + u8 res2[3]; + u8 urxh; +#else /* Little Endian */ + u8 utxh; + u8 res1[3]; + u8 urxh; + u8 res2[3]; +#endif + u32 ubrdiv; +}; + + +/* PWM TIMER (see manual chapter 10) */ +struct s3c24x0_timer { + u32 tcntb; + u32 tcmpb; + u32 tcnto; +}; + +struct s3c24x0_timers { + u32 tcfg0; + u32 tcfg1; + u32 tcon; + struct s3c24x0_timer ch[4]; + u32 tcntb4; + u32 tcnto4; +}; + + +/* USB DEVICE (see manual chapter 13) */ +struct s3c24x0_usb_dev_fifos { +#ifdef __BIG_ENDIAN + u8 res[3]; + u8 ep_fifo_reg; +#else /* little endian */ + u8 ep_fifo_reg; + u8 res[3]; +#endif +}; + +struct s3c24x0_usb_dev_dmas { +#ifdef __BIG_ENDIAN + u8 res1[3]; + u8 ep_dma_con; + u8 res2[3]; + u8 ep_dma_unit; + u8 res3[3]; + u8 ep_dma_fifo; + u8 res4[3]; + u8 ep_dma_ttc_l; + u8 res5[3]; + u8 ep_dma_ttc_m; + u8 res6[3]; + u8 ep_dma_ttc_h; +#else /* little endian */ + u8 ep_dma_con; + u8 res1[3]; + u8 ep_dma_unit; + u8 res2[3]; + u8 ep_dma_fifo; + u8 res3[3]; + u8 ep_dma_ttc_l; + u8 res4[3]; + u8 ep_dma_ttc_m; + u8 res5[3]; + u8 ep_dma_ttc_h; + u8 res6[3]; +#endif +}; + +struct s3c24x0_usb_device { +#ifdef __BIG_ENDIAN + u8 res1[3]; + u8 func_addr_reg; + u8 res2[3]; + u8 pwr_reg; + u8 res3[3]; + u8 ep_int_reg; + u8 res4[15]; + u8 usb_int_reg; + u8 res5[3]; + u8 ep_int_en_reg; + u8 res6[15]; + u8 usb_int_en_reg; + u8 res7[3]; + u8 frame_num1_reg; + u8 res8[3]; + u8 frame_num2_reg; + u8 res9[3]; + u8 index_reg; + u8 res10[7]; + u8 maxp_reg; + u8 res11[3]; + u8 ep0_csr_in_csr1_reg; + u8 res12[3]; + u8 in_csr2_reg; + u8 res13[7]; + u8 out_csr1_reg; + u8 res14[3]; + u8 out_csr2_reg; + u8 res15[3]; + u8 out_fifo_cnt1_reg; + u8 res16[3]; + u8 out_fifo_cnt2_reg; +#else /* little endian */ + u8 func_addr_reg; + u8 res1[3]; + u8 pwr_reg; + u8 res2[3]; + u8 ep_int_reg; + u8 res3[15]; + u8 usb_int_reg; + u8 res4[3]; + u8 ep_int_en_reg; + u8 res5[15]; + u8 usb_int_en_reg; + u8 res6[3]; + u8 frame_num1_reg; + u8 res7[3]; + u8 frame_num2_reg; + u8 res8[3]; + u8 index_reg; + u8 res9[7]; + u8 maxp_reg; + u8 res10[7]; + u8 ep0_csr_in_csr1_reg; + u8 res11[3]; + u8 in_csr2_reg; + u8 res12[3]; + u8 out_csr1_reg; + u8 res13[7]; + u8 out_csr2_reg; + u8 res14[3]; + u8 out_fifo_cnt1_reg; + u8 res15[3]; + u8 out_fifo_cnt2_reg; + u8 res16[3]; +#endif /* __BIG_ENDIAN */ + struct s3c24x0_usb_dev_fifos fifo[5]; + struct s3c24x0_usb_dev_dmas dma[5]; +}; + + +/* WATCH DOG TIMER (see manual chapter 18) */ +struct s3c24x0_watchdog { + u32 wtcon; + u32 wtdat; + u32 wtcnt; +}; + +/* IIS (see manual chapter 21) */ +struct s3c24x0_i2s { +#ifdef __BIG_ENDIAN + u16 res1; + u16 iiscon; + u16 res2; + u16 iismod; + u16 res3; + u16 iispsr; + u16 res4; + u16 iisfcon; + u16 res5; + u16 iisfifo; +#else /* little endian */ + u16 iiscon; + u16 res1; + u16 iismod; + u16 res2; + u16 iispsr; + u16 res3; + u16 iisfcon; + u16 res4; + u16 iisfifo; + u16 res5; +#endif +}; + + +/* I/O PORT (see manual chapter 9) */ +struct s3c24x0_gpio { +#ifdef CONFIG_S3C2400 + u32 pacon; + u32 padat; + + u32 pbcon; + u32 pbdat; + u32 pbup; + + u32 pccon; + u32 pcdat; + u32 pcup; + + u32 pdcon; + u32 pddat; + u32 pdup; + + u32 pecon; + u32 pedat; + u32 peup; + + u32 pfcon; + u32 pfdat; + u32 pfup; + + u32 pgcon; + u32 pgdat; + u32 pgup; + + u32 opencr; + + u32 misccr; + u32 extint; +#endif +#ifdef CONFIG_S3C2410 + u32 gpacon; + u32 gpadat; + u32 res1[2]; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; + u32 res2; + u32 gpccon; + u32 gpcdat; + u32 gpcup; + u32 res3; + u32 gpdcon; + u32 gpddat; + u32 gpdup; + u32 res4; + u32 gpecon; + u32 gpedat; + u32 gpeup; + u32 res5; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; + u32 res6; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; + u32 res7; + u32 gphcon; + u32 gphdat; + u32 gphup; + u32 res8; + + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; +#endif +#if defined(CONFIG_S3C2440) + u32 gpacon; + u32 gpadat; + u32 res1[2]; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; + u32 res2; + u32 gpccon; + u32 gpcdat; + u32 gpcup; + u32 res3; + u32 gpdcon; + u32 gpddat; + u32 gpdup; + u32 res4; + u32 gpecon; + u32 gpedat; + u32 gpeup; + u32 res5; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; + u32 res6; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; + u32 res7; + u32 gphcon; + u32 gphdat; + u32 gphup; + u32 res8; + + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; + + u32 res9; + u32 dsc0; + u32 dsc1; + u32 mslcon; + u32 gpjcon; + u32 gpjdat; + u32 gpjup; + u32 res10; +#endif +}; + + +/* RTC (see manual chapter 17) */ +struct s3c24x0_rtc { +#ifdef __BIG_ENDIAN + u8 res1[67]; + u8 rtccon; + u8 res2[3]; + u8 ticnt; + u8 res3[11]; + u8 rtcalm; + u8 res4[3]; + u8 almsec; + u8 res5[3]; + u8 almmin; + u8 res6[3]; + u8 almhour; + u8 res7[3]; + u8 almdate; + u8 res8[3]; + u8 almmon; + u8 res9[3]; + u8 almyear; + u8 res10[3]; + u8 rtcrst; + u8 res11[3]; + u8 bcdsec; + u8 res12[3]; + u8 bcdmin; + u8 res13[3]; + u8 bcdhour; + u8 res14[3]; + u8 bcddate; + u8 res15[3]; + u8 bcdday; + u8 res16[3]; + u8 bcdmon; + u8 res17[3]; + u8 bcdyear; +#else /* little endian */ + u8 res0[64]; + u8 rtccon; + u8 res1[3]; + u8 ticnt; + u8 res2[11]; + u8 rtcalm; + u8 res3[3]; + u8 almsec; + u8 res4[3]; + u8 almmin; + u8 res5[3]; + u8 almhour; + u8 res6[3]; + u8 almdate; + u8 res7[3]; + u8 almmon; + u8 res8[3]; + u8 almyear; + u8 res9[3]; + u8 rtcrst; + u8 res10[3]; + u8 bcdsec; + u8 res11[3]; + u8 bcdmin; + u8 res12[3]; + u8 bcdhour; + u8 res13[3]; + u8 bcddate; + u8 res14[3]; + u8 bcdday; + u8 res15[3]; + u8 bcdmon; + u8 res16[3]; + u8 bcdyear; + u8 res17[3]; +#endif +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2400_adc { + u32 adccon; + u32 adcdat; +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2410_adc { + u32 adccon; + u32 adctsc; + u32 adcdly; + u32 adcdat0; + u32 adcdat1; +}; + + +/* SPI (see manual chapter 22) */ +struct s3c24x0_spi_channel { + u8 spcon; + u8 res1[3]; + u8 spsta; + u8 res2[3]; + u8 sppin; + u8 res3[3]; + u8 sppre; + u8 res4[3]; + u8 sptdat; + u8 res5[3]; + u8 sprdat; + u8 res6[3]; + u8 res7[16]; +}; + +struct s3c24x0_spi { + struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; +}; + + +/* MMC INTERFACE (see S3C2400 manual chapter 19) */ +struct s3c2400_mmc { +#ifdef __BIG_ENDIAN + u8 res1[3]; + u8 mmcon; + u8 res2[3]; + u8 mmcrr; + u8 res3[3]; + u8 mmfcon; + u8 res4[3]; + u8 mmsta; + u16 res5; + u16 mmfsta; + u8 res6[3]; + u8 mmpre; + u16 res7; + u16 mmlen; + u8 res8[3]; + u8 mmcr7; + u32 mmrsp[4]; + u8 res9[3]; + u8 mmcmd0; + u32 mmcmd1; + u16 res10; + u16 mmcr16; + u8 res11[3]; + u8 mmdat; +#else + u8 mmcon; + u8 res1[3]; + u8 mmcrr; + u8 res2[3]; + u8 mmfcon; + u8 res3[3]; + u8 mmsta; + u8 res4[3]; + u16 mmfsta; + u16 res5; + u8 mmpre; + u8 res6[3]; + u16 mmlen; + u16 res7; + u8 mmcr7; + u8 res8[3]; + u32 mmrsp[4]; + u8 mmcmd0; + u8 res9[3]; + u32 mmcmd1; + u16 mmcr16; + u16 res10; + u8 mmdat; + u8 res11[3]; +#endif +}; + + +/* SD INTERFACE (see S3C2410 manual chapter 19) */ +struct s3c2410_sdi { + u32 sdicon; + u32 sdipre; + u32 sdicarg; + u32 sdiccon; + u32 sdicsta; + u32 sdirsp0; + u32 sdirsp1; + u32 sdirsp2; + u32 sdirsp3; + u32 sdidtimer; + u32 sdibsize; + u32 sdidcon; + u32 sdidcnt; + u32 sdidsta; + u32 sdifsta; +#ifdef __BIG_ENDIAN + u8 res[3]; + u8 sdidat; +#else + u8 sdidat; + u8 res[3]; +#endif + u32 sdiimsk; +}; + +#endif /*__S3C24X0_H__*/ diff --git a/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h new file mode 100644 index 00000000..393cc9d9 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef CONFIG_S3C2400 + #include <asm/arch/s3c2400.h> +#elif defined CONFIG_S3C2410 + #include <asm/arch/s3c2410.h> +#elif defined CONFIG_S3C2440 + #include <asm/arch/s3c2440.h> +#else + #error Please define the s3c24x0 cpu type +#endif |