diff options
Diffstat (limited to 'roms/u-boot/arch/arm/include/asm/arch-armv7')
4 files changed, 149 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h new file mode 100644 index 00000000..6a19950d --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _GLOBALTIMER_H_ +#define _GLOBALTIMER_H_ + +struct globaltimer { + u32 cnt_l; /* 0x00 */ + u32 cnt_h; + u32 ctl; + u32 stat; + u32 cmp_l; /* 0x10 */ + u32 cmp_h; + u32 inc; +}; + +#endif /* _GLOBALTIMER_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h new file mode 100644 index 00000000..34e88a8f --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, <matt.waddel@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SYSCTRL_H_ +#define _SYSCTRL_H_ + +/* System controller (SP810) register definitions */ +#define SP810_TIMER0_ENSEL (1 << 15) +#define SP810_TIMER1_ENSEL (1 << 17) +#define SP810_TIMER2_ENSEL (1 << 19) +#define SP810_TIMER3_ENSEL (1 << 21) + +struct sysctrl { + u32 scctrl; /* 0x000 */ + u32 scsysstat; + u32 scimctrl; + u32 scimstat; + u32 scxtalctrl; + u32 scpllctrl; + u32 scpllfctrl; + u32 scperctrl0; + u32 scperctrl1; + u32 scperen; + u32 scperdis; + u32 scperclken; + u32 scperstat; + u32 res1[0x006]; + u32 scflashctrl; /* 0x04c */ + u32 res2[0x3a4]; + u32 scsysid0; /* 0xee0 */ + u32 scsysid1; + u32 scsysid2; + u32 scsysid3; + u32 scitcr; + u32 scitir0; + u32 scitir1; + u32 scitor; + u32 sccntctrl; + u32 sccntdata; + u32 sccntstep; + u32 res3[0x32]; + u32 scperiphid0; /* 0xfe0 */ + u32 scperiphid1; + u32 scperiphid2; + u32 scperiphid3; + u32 scpcellid0; + u32 scpcellid1; + u32 scpcellid2; + u32 scpcellid3; +}; +#endif /* _SYSCTRL_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h new file mode 100644 index 00000000..a0412bd3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2010 Linaro + * Matt Waddel, <matt.waddel@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SYSTIMER_H_ +#define _SYSTIMER_H_ + +/* AMBA timer register base address */ +#define SYSTIMER_BASE 0x10011000 + +#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ +#define SYSTIMER_RELOAD 0xFFFFFFFF +#define SYSTIMER_EN (1 << 7) +#define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) + +struct systimer { + u32 timer0load; /* 0x00 */ + u32 timer0value; + u32 timer0control; + u32 timer0intclr; + u32 timer0ris; + u32 timer0mis; + u32 timer0bgload; + u32 timer1load; /* 0x20 */ + u32 timer1value; + u32 timer1control; + u32 timer1intclr; + u32 timer1ris; + u32 timer1mis; + u32 timer1bgload; +}; +#endif /* _SYSTIMER_H_ */ diff --git a/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h b/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h new file mode 100644 index 00000000..4483b1a3 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2010 + * Matt Waddel, <matt.waddel@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _WDT_H_ +#define _WDT_H_ + +/* Watchdog timer (SP805) register base address */ +#define WDT_BASE 0x100E5000 + +#define WDT_EN 0x2 +#define WDT_RESET_LOAD 0x0 + +struct wdt { + u32 wdogload; /* 0x000 */ + u32 wdogvalue; + u32 wdogcontrol; + u32 wdogintclr; + u32 wdogris; + u32 wdogmis; + u32 res1[0x2F9]; + u32 wdoglock; /* 0xC00 */ + u32 res2[0xBE]; + u32 wdogitcr; /* 0xF00 */ + u32 wdogitop; + u32 res3[0x35]; + u32 wdogperiphid0; /* 0xFE0 */ + u32 wdogperiphid1; + u32 wdogperiphid2; + u32 wdogperiphid3; + u32 wdogpcellid0; + u32 wdogpcellid1; + u32 wdogpcellid2; + u32 wdogpcellid3; +}; + +#endif /* _WDT_H_ */ |