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-rw-r--r--roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile14
-rw-r--r--roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S30
-rw-r--r--roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c327
-rw-r--r--roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S32
4 files changed, 403 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile
new file mode 100644
index 00000000..9f43ded1
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cache.o
+obj-y += reset.o
+
+obj-y += clock.o
diff --git a/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S
new file mode 100644
index 00000000..3089592e
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * based on arch/arm/cpu/armv7/omap3/cache.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.align 5
+
+#include <linux/linkage.h>
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ENTRY(v7_outer_cache_enable)
+ push {r0, r1, r2, lr}
+ mrc 15, 0, r3, cr1, cr0, 1
+ orr r3, r3, #2
+ mcr 15, 0, r3, cr1, cr0, 1
+ pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_enable)
+
+ENTRY(v7_outer_cache_disable)
+ push {r0, r1, r2, lr}
+ mrc 15, 0, r3, cr1, cr0, 1
+ bic r3, r3, #2
+ mcr 15, 0, r3, cr1, cr0, 1
+ pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_disable)
+#endif
diff --git a/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c
new file mode 100644
index 00000000..3da00717
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#define CLK_M 0
+#define CLK_D 1
+#define CLK_P 2
+
+#ifndef CONFIG_SYS_CLK_FREQ_C100
+#define CONFIG_SYS_CLK_FREQ_C100 12000000
+#endif
+#ifndef CONFIG_SYS_CLK_FREQ_C110
+#define CONFIG_SYS_CLK_FREQ_C110 24000000
+#endif
+
+/* s5pc110: return pll clock frequency */
+static unsigned long s5pc100_get_pll_clk(int pllreg)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case HPLL:
+ r = readl(&clk->hpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [23:16]
+ * EPLL_CON: MIDV [23:16]
+ * HPLL_CON: MIDV [23:16]
+ */
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x0ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ freq = CONFIG_SYS_CLK_FREQ_C100;
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc100: return pll clock frequency */
+static unsigned long s5pc110_get_pll_clk(int pllreg)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C110;
+ if (pllreg == APLL) {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ } else
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc110: return ARM clock frequency */
+static unsigned long s5pc110_get_arm_clk(void)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div0);
+
+ /* APLL_RATIO: [2:0] */
+ apll_ratio = div & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll;
+
+ return armclk;
+}
+
+/* s5pc100: return ARM clock frequency */
+static unsigned long s5pc100_get_arm_clk(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio, arm_ratio;
+
+ div = readl(&clk->div0);
+
+ /* ARM_RATIO: [6:4] */
+ arm_ratio = (div >> 4) & 0x7;
+ /* APLL_RATIO: [0] */
+ apll_ratio = div & 0x1;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll / (arm_ratio + 1);
+
+ return armclk;
+}
+
+/* s5pc100: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = readl(&clk->div0);
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* s5pc100: return PCLKD1 frequency */
+static unsigned long get_pclkd1(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long d1_bus, pclkd1;
+ uint div, d1_bus_ratio, pclkd1_ratio;
+
+ div = readl(&clk->div0);
+ /* D1_BUS_RATIO: [14:12] */
+ d1_bus_ratio = (div >> 12) & 0x7;
+ /* PCLKD1_RATIO: [18:16] */
+ pclkd1_ratio = (div >> 16) & 0x7;
+
+ /* ASYNC Mode */
+ d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
+ pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+ return pclkd1;
+}
+
+/* s5pc110: return HCLKs frequency */
+static unsigned long get_hclk_sys(int dom)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long hclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int hclk_sys_ratio;
+
+ if (dom == CLK_M)
+ return get_hclk();
+
+ div = readl(&clk->div0);
+
+ /*
+ * HCLK_MSYS_RATIO: [10:8]
+ * HCLK_DSYS_RATIO: [19:16]
+ * HCLK_PSYS_RATIO: [27:24]
+ */
+ offset = 8 + (dom << 0x3);
+
+ hclk_sys_ratio = (div >> offset) & 0xf;
+
+ hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+ return hclk;
+}
+
+/* s5pc110: return PCLKs frequency */
+static unsigned long get_pclk_sys(int dom)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int pclk_sys_ratio;
+
+ div = readl(&clk->div0);
+
+ /*
+ * PCLK_MSYS_RATIO: [14:12]
+ * PCLK_DSYS_RATIO: [22:20]
+ * PCLK_PSYS_RATIO: [30:28]
+ */
+ offset = 12 + (dom << 0x3);
+
+ pclk_sys_ratio = (div >> offset) & 0x7;
+
+ pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
+
+ return pclk;
+}
+
+/* s5pc110: return peripheral clock frequency */
+static unsigned long s5pc110_get_pclk(void)
+{
+ return get_pclk_sys(CLK_P);
+}
+
+/* s5pc100: return peripheral clock frequency */
+static unsigned long s5pc100_get_pclk(void)
+{
+ return get_pclkd1();
+}
+
+/* s5pc1xx: return uart clock frequency */
+static unsigned long s5pc1xx_get_uart_clk(int dev_index)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pclk();
+ else
+ return s5pc100_get_pclk();
+}
+
+/* s5pc1xx: return pwm clock frequency */
+static unsigned long s5pc1xx_get_pwm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pclk();
+ else
+ return s5pc100_get_pclk();
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pll_clk(pllreg);
+ else
+ return s5pc100_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_arm_clk();
+ else
+ return s5pc100_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc1xx_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc1xx_get_uart_clk(dev_index);
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ /* Do NOTHING */
+}
diff --git a/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S
new file mode 100644
index 00000000..bd74f2b4
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <linux/linkage.h>
+
+#define S5PC100_SWRESET 0xE0200000
+#define S5PC110_SWRESET 0xE0102000
+
+ENTRY(reset_cpu)
+ ldr r1, =S5PC100_PRO_ID
+ ldr r2, [r1]
+ ldr r4, =0x00010000
+ and r4, r2, r4
+ cmp r4, #0
+ bne 110f
+ /* S5PC100 */
+ ldr r1, =S5PC100_SWRESET
+ ldr r2, =0xC100
+ b 200f
+110: /* S5PC110 */
+ ldr r1, =S5PC110_SWRESET
+ mov r2, #1
+200:
+ str r2, [r1]
+_loop_forever:
+ b _loop_forever
+ENDPROC(reset_cpu)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-11 04:38:45 +0000