Initial import of qemu-2.4.1HEADmaster

2 files changed, 183 insertions, 0 deletions

diff --git a/roms/u-boot/nand_spl/board/freescale/p1023rds/Makefile b/roms/u-boot/nand_spl/board/freescale/p1023rds/Makefile
new file mode 100644
index 00000000..fba9f935
--- /dev/null
+++ b/roms/u-boot/nand_spl/board/freescale/p1023rds/Makefile
@@ -0,0 +1,87 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PAD_TO := 0xfff01000
+
+nandobj	:= $(objtree)/nand_spl/
+
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
+		$(LDFLAGS) $(LDFLAGS_FINAL)
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
+
+SOBJS	= start.o resetvec.o
+COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(nandobj)board/$(BOARDDIR)
+
+targets += $(__OBJS)
+
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map -o $@
+
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+		-ansi -D__ASSEMBLY__ -P - <$< >$@
+
+# create symbolic links for common files
+
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
+
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
+
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
+
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
+
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
+
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
+
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
+
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
+
+$(obj)/start.S:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/start.S $@
+
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
+
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/roms/u-boot/nand_spl/board/freescale/p1023rds/nand_boot.c b/roms/u-boot/nand_spl/board/freescale/p1023rds/nand_boot.c
new file mode 100644
index 00000000..d9afa6d0
--- /dev/null
+++ b/roms/u-boot/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+void sdram_init(void)
+{
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
+
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
+	__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
+	__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
+	/* Set, but do not enable the memory */
+	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+	asm volatile("sync;isync");
+	udelay(500);
+
+	/* Let the controller go */
+	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+	/* Initialize the DDR3 */
+	sdram_init();
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}