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| author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
| commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
| tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/xilinx/microblaze-generic | |
| download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip | |
Diffstat (limited to 'roms/u-boot/board/xilinx/microblaze-generic')
4 files changed, 208 insertions, 0 deletions
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/Makefile b/roms/u-boot/board/xilinx/microblaze-generic/Makefile new file mode 100644 index 00000000..22c8bef1 --- /dev/null +++ b/roms/u-boot/board/xilinx/microblaze-generic/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = microblaze-generic.o diff --git a/roms/u-boot/board/xilinx/microblaze-generic/config.mk b/roms/u-boot/board/xilinx/microblaze-generic/config.mk new file mode 100644 index 00000000..36bdd963 --- /dev/null +++ b/roms/u-boot/board/xilinx/microblaze-generic/config.mk @@ -0,0 +1,18 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK <monstr@monstr.eu> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# CAUTION: This file is a faked configuration !!! +# There is no real target for the microblaze-generic +# configuration. You have to replace this file with +# the generated file from your Xilinx design flow. +# + +CONFIG_SYS_TEXT_BASE = 0x29000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c new file mode 100644 index 00000000..42a8d0c4 --- /dev/null +++ b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ + +#include <common.h> +#include <config.h> +#include <netdev.h> +#include <asm/processor.h> +#include <asm/microblaze_intc.h> +#include <asm/asm.h> +#include <asm/gpio.h> + +#ifdef CONFIG_XILINX_GPIO +static int reset_pin = -1; +#endif + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_XILINX_GPIO + if (reset_pin != -1) + gpio_direction_output(reset_pin, 1); +#endif + +#ifdef CONFIG_XILINX_TB_WATCHDOG + hw_watchdog_disable(); +#endif + + puts ("Reseting board\n"); + __asm__ __volatile__ (" mts rmsr, r0;" \ + "bra r0"); + + return 0; +} + +int gpio_init (void) +{ +#ifdef CONFIG_XILINX_GPIO + reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); + if (reset_pin != -1) + gpio_request(reset_pin, "reset_pin"); +#endif + return 0; +} + +void board_init(void) +{ + gpio_init(); +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif + +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + +#ifdef CONFIG_XILINX_LL_TEMAC +# ifdef XILINX_LLTEMAC_BASEADDR +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# endif +# endif +# endif +# ifdef XILINX_LLTEMAC_BASEADDR1 +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# endif +# endif +# endif +#endif + + return ret; +} diff --git a/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h b/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h new file mode 100644 index 00000000..d6d0d679 --- /dev/null +++ b/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * CAUTION: This file is a faked configuration !!! + * There is no real target for the microblaze-generic + * configuration. You have to replace this file with + * the generated file from your Xilinx design flow. + */ + +#define XILINX_BOARD_NAME microblaze-generic + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_FSL_NUMBER 3 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 6 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 0 + +/* Uart pheriphery is RS232_Uart */ +#define XILINX_UARTLITE_BASEADDR 0x40600000 +#define XILINX_UARTLITE_BAUDRATE 115200 + +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* Flash Memory is FLASH_2Mx32 */ +#define XILINX_FLASH_START 0x2c000000 +#define XILINX_FLASH_SIZE 0x00800000 + +/* Main Memory is DDR_SDRAM_64Mx32 */ +#define XILINX_RAM_START 0x28000000 +#define XILINX_RAM_SIZE 0x04000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XILINX_EMACLITE_BASEADDR 0x40C00000 + +/* LL_TEMAC Ethernet controller */ +#define XILINX_LLTEMAC_BASEADDR 0x44000000 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 +#define XILINX_LLTEMAC_BASEADDR1 0x44200000 +#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 + +/* Watchdog IP is wxi_timebase_wdt_0 */ +#define XILINX_WATCHDOG_BASEADDR 0x50000000 +#define XILINX_WATCHDOG_IRQ 1 |