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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/spear/spear300 | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/board/spear/spear300')
-rw-r--r-- | roms/u-boot/board/spear/spear300/Makefile | 8 | ||||
-rw-r--r-- | roms/u-boot/board/spear/spear300/spear300.c | 60 |
2 files changed, 68 insertions, 0 deletions
diff --git a/roms/u-boot/board/spear/spear300/Makefile b/roms/u-boot/board/spear/spear300/Makefile new file mode 100644 index 00000000..84d05e33 --- /dev/null +++ b/roms/u-boot/board/spear/spear300/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := spear300.o diff --git a/roms/u-boot/board/spear/spear300/spear300.c b/roms/u-boot/board/spear/spear300/spear300.c new file mode 100644 index 00000000..6b6bd9f2 --- /dev/null +++ b/roms/u-boot/board/spear/spear300/spear300.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init() +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + +#if defined(CONFIG_NAND_FSMC) + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + fsmc_nand_init(nand); + } +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) + ret++; +#endif + return ret; +} |