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| author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
| commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
| tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h | |
| download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip | |
Diffstat (limited to 'roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h')
| -rw-r--r-- | roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h b/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 00000000..13aebbd8 --- /dev/null +++ b/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ |