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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/freescale/p2020come/ddr.c | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/board/freescale/p2020come/ddr.c')
-rw-r--r-- | roms/u-boot/board/freescale/p2020come/ddr.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/p2020come/ddr.c b/roms/u-boot/board/freescale/p2020come/ddr.c new file mode 100644 index 00000000..b642e125 --- /dev/null +++ b/roms/u-boot/board/freescale/p2020come/ddr.c @@ -0,0 +1,29 @@ +/* + * Copyright 2009, 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + if (!pdimm->n_ranks) + return; + + /* + * Set DDR_SDRAM_CLK_CNTL = 0x02800000 + * + * Clock is launched 5/8 applied cycle after address/command + */ + popts->clk_adjust = 5; +} |