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authorfishsoupisgood <github@madingley.org>2019-04-29 01:17:54 +0100
committerfishsoupisgood <github@madingley.org>2019-05-27 03:43:43 +0100
commit3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch)
tree65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/eXalion/eXalion.h
downloadqemu-master.tar.gz
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Initial import of qemu-2.4.1HEADmaster
Diffstat (limited to 'roms/u-boot/board/eXalion/eXalion.h')
-rw-r--r--roms/u-boot/board/eXalion/eXalion.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/roms/u-boot/board/eXalion/eXalion.h b/roms/u-boot/board/eXalion/eXalion.h
new file mode 100644
index 00000000..7804f4f2
--- /dev/null
+++ b/roms/u-boot/board/eXalion/eXalion.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EXALION_H
+#define __EXALION_H
+
+/* IRQ settings */
+#define PCI_INT_NA (0xff) /* PCI Intr. not used */
+#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */
+#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */
+#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */
+#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */
+#if defined (CPU_MPC8245)
+#define LN_1_INT PCI_INT_B /* ethernet interrupt level */
+#define LN_2_INT PCI_INT_C /* ethernet interrupt level */
+#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */
+#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */
+#elif defined (CPU_MPC8240)
+#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */
+#define LN_INT PCI_INT_C /* ethernet interrupt level */
+#endif
+
+#ifndef __ASSEMBLY__
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __EXALION_H */