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| author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
| commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
| tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/board/a3m071/is46r16320d.h | |
| download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip | |
Diffstat (limited to 'roms/u-boot/board/a3m071/is46r16320d.h')
| -rw-r--r-- | roms/u-boot/board/a3m071/is46r16320d.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/roms/u-boot/board/a3m071/is46r16320d.h b/roms/u-boot/board/a3m071/is46r16320d.h new file mode 100644 index 00000000..981359f2 --- /dev/null +++ b/roms/u-boot/board/a3m071/is46r16320d.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SDRAM_DDR /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ + +/* SDRAM Config Standard timing */ +#define SDRAM_MODE 0x008d0000 +#define SDRAM_EMODE 0x40010000 +#define SDRAM_CONTROL 0x70430f00 +#define SDRAM_CONFIG1 0x33622930 +#define SDRAM_CONFIG2 0x46670000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif |