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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/x86/include/asm/cache.h | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/arch/x86/include/asm/cache.h')
-rw-r--r-- | roms/u-boot/arch/x86/include/asm/cache.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/include/asm/cache.h b/roms/u-boot/arch/x86/include/asm/cache.h new file mode 100644 index 00000000..508b63f5 --- /dev/null +++ b/roms/u-boot/arch/x86/include/asm/cache.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __X86_CACHE_H__ +#define __X86_CACHE_H__ + +/* + * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise + * use 64-bytes, a safe default for x86. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + +static inline void wbinvd(void) +{ + asm volatile ("wbinvd" : : : "memory"); +} + +static inline void invd(void) +{ + asm volatile("invd" : : : "memory"); +} + +/* Enable caches and write buffer */ +void enable_caches(void); + +/* Disable caches and write buffer */ +void disable_caches(void); + +#endif /* __X86_CACHE_H__ */ |