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authorfishsoupisgood <github@madingley.org>2019-04-29 01:17:54 +0100
committerfishsoupisgood <github@madingley.org>2019-05-27 03:43:43 +0100
commit3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch)
tree65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/sh/include/asm/cpu_sh3.h
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Initial import of qemu-2.4.1HEADmaster
Diffstat (limited to 'roms/u-boot/arch/sh/include/asm/cpu_sh3.h')
-rw-r--r--roms/u-boot/arch/sh/include/asm/cpu_sh3.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/roms/u-boot/arch/sh/include/asm/cpu_sh3.h b/roms/u-boot/arch/sh/include/asm/cpu_sh3.h
new file mode 100644
index 00000000..0c85e94f
--- /dev/null
+++ b/roms/u-boot/arch/sh/include/asm/cpu_sh3.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_CPU_SH3_H_
+#define _ASM_CPU_SH3_H_
+
+/* cache control */
+#define CCR_CACHE_STOP 0x00000008
+#define CCR_CACHE_ENABLE 0x00000005
+#define CCR_CACHE_ICI 0x00000008
+
+#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
+#define CACHE_OC_WAY_SHIFT 13
+#define CACHE_OC_NUM_ENTRIES 256
+#define CACHE_OC_ENTRY_SHIFT 4
+
+#if defined(CONFIG_CPU_SH7706)
+#include <asm/cpu_sh7706.h>
+#elif defined(CONFIG_CPU_SH7710)
+#include <asm/cpu_sh7710.h>
+#elif defined(CONFIG_CPU_SH7720)
+#include <asm/cpu_sh7720.h>
+#else
+#error "Unknown SH3 variant"
+#endif
+
+#endif /* _ASM_CPU_SH3_H_ */