Initial import of qemu-2.4.1HEADmaster

7 files changed, 303 insertions, 0 deletions

diff --git a/roms/u-boot/arch/sh/cpu/sh2/Makefile b/roms/u-boot/arch/sh/cpu/sh2/Makefile
new file mode 100644
index 00000000..a19ed5ec
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# Copyright (C) 2008 Renesas Solutions Corp.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= cpu.o interrupts.o watchdog.o
diff --git a/roms/u-boot/arch/sh/cpu/sh2/config.mk b/roms/u-boot/arch/sh/cpu/sh2/config.mk
new file mode 100644
index 00000000..4904d76d
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2007-2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+#
+ENDIANNESS += -EB
+
+ifdef CONFIG_SH2A
+PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb
+else # SH2
+PLATFORM_CPPFLAGS += -m3e -mb
+endif
+PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic)
+
+PLATFORM_LDFLAGS += $(ENDIANNESS)
diff --git a/roms/u-boot/arch/sh/cpu/sh2/cpu.c b/roms/u-boot/arch/sh/cpu/sh2/cpu.c
new file mode 100644
index 00000000..a2f856f4
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/cpu.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#define STBCR4      0xFFFE040C
+#define cmt_clock_enable() do {\
+		writeb(readb(STBCR4) & ~0x04, STBCR4);\
+	} while (0)
+#define scif0_enable() do {\
+		writeb(readb(STBCR4) & ~0x80, STBCR4);\
+	} while (0)
+#define scif3_enable() do {\
+		writeb(readb(STBCR4) & ~0x10, STBCR4);\
+	} while (0)
+
+int checkcpu(void)
+{
+	puts("CPU: SH2\n");
+	return 0;
+}
+
+int cpu_init(void)
+{
+	/* SCIF enable */
+#if defined(CONFIG_CONS_SCIF3)
+	scif3_enable();
+#else
+	scif0_enable();
+#endif
+	/* CMT clock enable */
+	cmt_clock_enable() ;
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+	reset_cpu(0);
+	return 0;
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+	return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/arch/sh/cpu/sh2/interrupts.c b/roms/u-boot/arch/sh/cpu/sh2/interrupts.c
new file mode 100644
index 00000000..e06f9bb9
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/interrupts.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/arch/sh/cpu/sh2/start.S b/roms/u-boot/arch/sh/cpu/sh2/start.S
new file mode 100644
index 00000000..5b92a015
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/start.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Renesas Solutions Corp.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+	.text
+	.align	2
+
+	.global	_start
+_sh_start:
+	.long 0x00000010	/* Ppower ON reset PC*/
+	.long 0x00000000
+	.long 0x00000010	/* Manual reset PC */
+	.long 0x00000000
+_init:
+	mov.l	._lowlevel_init, r0
+100:	bsrf	r0
+	nop
+	bsr	1f
+	nop
+1:	sts	pr, r5
+	mov.l	._reloc_dst, r4
+	add	#(_sh_start-1b), r5
+	mov.l	._reloc_dst_end, r6
+
+2:	mov.l	@r5+, r1
+	mov.l	r1, @r4
+	add	#4, r4
+	cmp/hs	r6, r4
+	bf	2b
+
+	mov.l	._bss_start, r4
+	mov.l	._bss_end, r5
+	mov	#0, r1
+
+3:	mov.l	r1, @r4			/* bss clear */
+	add	#4, r4
+	cmp/hs	r5, r4
+	bf	3b
+
+	mov.l	._gd_init, r13		/* global data */
+	mov.l	._stack_init, r15	/* stack */
+
+	mov.l	._sh_generic_init, r0
+	jsr	@r0
+	nop
+
+loop:
+	bra	loop
+
+	.align	2
+
+._lowlevel_init:	.long	(lowlevel_init - (100b + 4))
+._reloc_dst:		.long	reloc_dst
+._reloc_dst_end:	.long	reloc_dst_end
+._bss_start:		.long	bss_start
+._bss_end:		.long	bss_end
+._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
+._stack_init:	.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._sh_generic_init:	.long	sh_generic_init
diff --git a/roms/u-boot/arch/sh/cpu/sh2/u-boot.lds b/roms/u-boot/arch/sh/cpu/sh2/u-boot.lds
new file mode 100644
index 00000000..254d9f27
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/u-boot.lds
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	 * entry and reloct_dst will be provided via ldflags
+	 */
+	. = .;
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		KEEP(arch/sh/cpu/sh2/start.o	(.text))
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	PROVIDE (reloc_dst_end = .);
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (__bss_end = .);
+}
diff --git a/roms/u-boot/arch/sh/cpu/sh2/watchdog.c b/roms/u-boot/arch/sh/cpu/sh2/watchdog.c
new file mode 100644
index 00000000..2edee747
--- /dev/null
+++ b/roms/u-boot/arch/sh/cpu/sh2/watchdog.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2008,2010 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2008,2010 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+
+int watchdog_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(unsigned long ignored)
+{
+	/* Address error with SR.BL=1 first. */
+	trigger_address_error();
+
+	while (1)
+		;
+}