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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/powerpc/lib/cache.c | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/arch/powerpc/lib/cache.c')
-rw-r--r-- | roms/u-boot/arch/powerpc/lib/cache.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/roms/u-boot/arch/powerpc/lib/cache.c b/roms/u-boot/arch/powerpc/lib/cache.c new file mode 100644 index 00000000..8fc87d3a --- /dev/null +++ b/roms/u-boot/arch/powerpc/lib/cache.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/cache.h> +#include <watchdog.h> + +void flush_cache(ulong start_addr, ulong size) +{ +#ifndef CONFIG_5xx + ulong addr, start, end; + + start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + end = start_addr + size - 1; + + for (addr = start; (addr <= end) && (addr >= start); + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); + WATCHDOG_RESET(); + } + /* wait for all dcbst to complete on bus */ + asm volatile("sync" : : : "memory"); + + for (addr = start; (addr <= end) && (addr >= start); + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); + WATCHDOG_RESET(); + } + asm volatile("sync" : : : "memory"); + /* flush prefetch queue */ + asm volatile("isync" : : : "memory"); +#endif +} |