Initial import of qemu-2.4.1HEADmaster

8 files changed, 697 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h
new file mode 100644
index 00000000..1b2fdb79
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK
+#define __ASM_ARCH_CLOCK
+
+struct prcmu {
+	unsigned int armclkfix_mgt;
+	unsigned int armclk_mgt;
+	unsigned int svammdspclk_mgt;
+	unsigned int siammdspclk_mgt;
+	unsigned int reserved;
+	unsigned int sgaclk_mgt;
+	unsigned int uartclk_mgt;
+	unsigned int msp02clk_mgt;
+	unsigned int i2cclk_mgt;
+	unsigned int sdmmcclk_mgt;
+	unsigned int slimclk_mgt;
+	unsigned int per1clk_mgt;
+	unsigned int per2clk_mgt;
+	unsigned int per3clk_mgt;
+	unsigned int per5clk_mgt;
+	unsigned int per6clk_mgt;
+	unsigned int per7clk_mgt;
+	unsigned int lcdclk_mgt;
+	unsigned int reserved1;
+	unsigned int bmlclk_mgt;
+	unsigned int hsitxclk_mgt;
+	unsigned int hsirxclk_mgt;
+	unsigned int hdmiclk_mgt;
+	unsigned int apeatclk_mgt;
+	unsigned int apetraceclk_mgt;
+	unsigned int mcdeclk_mgt;
+	unsigned int ipi2cclk_mgt;
+	unsigned int dsialtclk_mgt;
+	unsigned int spare2clk_mgt;
+	unsigned int dmaclk_mgt;
+	unsigned int b2r2clk_mgt;
+	unsigned int tvclk_mgt;
+	unsigned int unused[82];
+	unsigned int tcr;
+	unsigned int unused1[23];
+	unsigned int ape_softrst;
+};
+
+extern void u8500_clock_enable(int periph, int kern, int cluster);
+
+void db8500_clocks_init(void);
+
+#endif /* __ASM_ARCH_CLOCK */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h
new file mode 100644
index 00000000..7c85a891
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ * Copyright (C) 2008 STMicroelectronics
+ *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DB8500_GPIO_H__
+#define __DB8500_GPIO_H__
+
+/* Alternate functions: function C is set in hw by setting both A and B */
+enum db8500_gpio_alt {
+	DB8500_GPIO_ALT_GPIO = 0,
+	DB8500_GPIO_ALT_A = 1,
+	DB8500_GPIO_ALT_B = 2,
+	DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
+};
+
+enum db8500_gpio_pull {
+	DB8500_GPIO_PULL_NONE,
+	DB8500_GPIO_PULL_UP,
+	DB8500_GPIO_PULL_DOWN
+};
+
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
+void db8500_gpio_make_input(unsigned gpio);
+int db8500_gpio_get_input(unsigned gpio);
+void db8500_gpio_make_output(unsigned gpio, int val);
+void db8500_gpio_set_output(unsigned gpio, int val);
+
+#endif /* __DB8500_GPIO_H__ */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
new file mode 100644
index 00000000..64957016
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot. Ported 2010 to U-boot by:
+ * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __DB8500_PINCFG_H
+#define __DB8500_PINCFG_H
+
+#include "db8500_gpio.h"
+
+/*
+ * U-boot info:
+ * SLPM (sleep mode) config will be ignored by U-boot but it is still
+ * possible to configure it in order to keep cut-n-paste compability
+ * with Linux kernel config.
+ *
+ * pin configurations are represented by 32-bit integers:
+ *
+ *	bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *	bit  9..10 - Alternate Function Selection
+ *	bit 11..12 - Pull up/down state
+ *	bit     13 - Sleep mode behaviour (not used in U-boot)
+ *	bit     14 - Direction
+ *	bit     15 - Value (if output)
+ *	bit 16..18 - SLPM pull up/down state (not used in U-boot)
+ *	bit 19..20 - SLPM direction (not used in U-boot)
+ *	bit 21..22 - SLPM Value (if output) (not used in U-boot)
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *		     pull up/down = disabled
+ *		     sleep mode = input/wakeup
+ *		     direction = input
+ *		     value = low
+ *		     SLPM direction = same as normal
+ *		     SLPM pull = same as normal
+ *		     SLPM value = same as normal
+ *
+ * PIN_CFG	   - default config with alternate function
+ * PIN_CFG_PULL	   - default config with alternate function and pull up/down
+ */
+
+/* Sleep mode */
+enum db8500_gpio_slpm {
+	DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_NOCHANGE,
+	DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
+};
+
+#define PIN_NUM_MASK		0x1ff
+#define PIN_NUM(x)		((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT		9
+#define PIN_ALT_MASK		(0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)		(((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO		(DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A		(DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B		(DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C		(DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT		11
+#define PIN_PULL_MASK		(0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)		(((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE		(DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP		(DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN		(DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT		13
+#define PIN_SLPM_MASK		(0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)		(((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT	(DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE	(DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+
+#define PIN_DIR_SHIFT		14
+#define PIN_DIR_MASK		(0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x)		(((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT		(0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT		(1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT		15
+#define PIN_VAL_MASK		(0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x)		(((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW		(0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH		(1 << PIN_VAL_SHIFT)
+
+#define PIN_SLPM_PULL_SHIFT	16
+#define PIN_SLPM_PULL_MASK	(0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)	\
+	(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE	\
+	((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP	\
+	((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN	\
+	((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT	19
+#define PIN_SLPM_DIR_MASK	(0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)		\
+	(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT	((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT	((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT	21
+#define PIN_SLPM_VAL_MASK	(0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)		\
+	(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW	((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH	((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN	(PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP	(PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL	(PIN_DIR_INPUT | PIN_PULL_NONE)
+#define PIN_OUTPUT_LOW		(PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH		(PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+#define PIN_SLPM_INPUT_PULLDOWN	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
+
+#define PIN_CFG_DEFAULT		(0)
+
+#define PIN_CFG(num, alt)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_INPUT(num, alt, pull)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
+#define PIN_CFG_PULL(num, alt, pull)	\
+	((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+/**
+ * db8500_gpio_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several GPIO pins.
+ */
+void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
+
+#endif
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h
new file mode 100644
index 00000000..afa5942c
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _UX500_GPIO_h
+#define _UX500_GPIO_h
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/u8500.h>
+
+#define GPIO_TOTAL_PINS                 268
+
+#define GPIO_PINS_PER_BLOCK	32
+#define GPIO_BLOCKS_COUNT       (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin)		(((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+
+
+struct gpio_register {
+	u32 gpio_dat;	/* data register : 0x000 */
+	u32 gpio_dats;	/* data Set register : 0x004 */
+	u32 gpio_datc;	/* data Clear register : 0x008 */
+	u32 gpio_pdis;	/* Pull disable register : 0x00C */
+	u32 gpio_dir;	/* data direction register : 0x010 */
+	u32 gpio_dirs;	/* data dir Set register : 0x014 */
+	u32 gpio_dirc;	/* data dir Clear register : 0x018 */
+	u32 gpio_slpm;	/* Sleep mode register : 0x01C */
+	u32 gpio_afsa;	/* AltFun A Select reg : 0x020 */
+	u32 gpio_afsb;	/* AltFun B Select reg : 0x024 */
+	u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
+	u32 reserved_1[(0x040 - 0x02C) >> 2];	/*0x028-0x3C Reserved*/
+	u32 gpio_rimsc;	/* rising edge intr set/clear : 0x040 */
+	u32 gpio_fimsc;	/* falling edge intr set/clear register : 0x044 */
+	u32 gpio_mis;	/* masked interrupt status register : 0x048 */
+	u32 gpio_ic;	/* Interrupt Clear register : 0x04C */
+	u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
+	u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
+	u32 gpio_wks;	/* Wakeup Status register : 0x058 */
+};
+
+/* Error values returned by functions */
+enum gpio_error {
+	GPIO_OK = 0,
+	GPIO_UNSUPPORTED_HW = -2,
+	GPIO_UNSUPPORTED_FEATURE = -3,
+	GPIO_INVALID_PARAMETER = -4,
+	GPIO_REQUEST_NOT_APPLICABLE = -5,
+	GPIO_REQUEST_PENDING = -6,
+	GPIO_NOT_CONFIGURED = -7,
+	GPIO_INTERNAL_ERROR = -8,
+	GPIO_INTERNAL_EVENT = 1,
+	GPIO_REMAINING_EVENT = 2,
+	GPIO_NO_MORE_PENDING_EVENT = 3,
+	GPIO_INVALID_CLIENT = -25,
+	GPIO_INVALID_PIN = -26,
+	GPIO_PIN_BUSY = -27,
+	GPIO_PIN_NOT_ALLOCATED = -28,
+	GPIO_WRONG_CLIENT = -29,
+	GPIO_UNSUPPORTED_ALTFUNC = -30,
+};
+
+/*GPIO DEVICE ID */
+enum gpio_device_id {
+	GPIO_DEVICE_ID_0,
+	GPIO_DEVICE_ID_1,
+	GPIO_DEVICE_ID_2,
+	GPIO_DEVICE_ID_3,
+	GPIO_DEVICE_ID_INVALID
+};
+
+/*
+ * Alternate Function:
+ *  refered in altfun_table to pointout particular altfun to be enabled
+ *  when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+enum gpio_alt_function {
+	GPIO_ALT_UART_0_MODEM,
+	GPIO_ALT_UART_0_NO_MODEM,
+	GPIO_ALT_UART_1,
+	GPIO_ALT_UART_2,
+	GPIO_ALT_I2C_0,
+	GPIO_ALT_I2C_1,
+	GPIO_ALT_I2C_2,
+	GPIO_ALT_I2C_3,
+	GPIO_ALT_MSP_0,
+	GPIO_ALT_MSP_1,
+	GPIO_ALT_MSP_2,
+	GPIO_ALT_MSP_3,
+	GPIO_ALT_MSP_4,
+	GPIO_ALT_MSP_5,
+	GPIO_ALT_SSP_0,
+	GPIO_ALT_SSP_1,
+	GPIO_ALT_MM_CARD0,
+	GPIO_ALT_SD_CARD0,
+	GPIO_ALT_DMA_0,
+	GPIO_ALT_DMA_1,
+	GPIO_ALT_HSI0,
+	GPIO_ALT_CCIR656_INPUT,
+	GPIO_ALT_CCIR656_OUTPUT,
+	GPIO_ALT_LCD_PANEL,
+	GPIO_ALT_MDIF,
+	GPIO_ALT_SDRAM,
+	GPIO_ALT_HAMAC_AUDIO_DBG,
+	GPIO_ALT_HAMAC_VIDEO_DBG,
+	GPIO_ALT_CLOCK_RESET,
+	GPIO_ALT_TSP,
+	GPIO_ALT_IRDA,
+	GPIO_ALT_USB_MINIMUM,
+	GPIO_ALT_USB_I2C,
+	GPIO_ALT_OWM,
+	GPIO_ALT_PWL,
+	GPIO_ALT_FSMC,
+	GPIO_ALT_COMP_FLASH,
+	GPIO_ALT_SRAM_NOR_FLASH,
+	GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+	GPIO_ALT_SCROLL_KEY,
+	GPIO_ALT_MSHC,
+	GPIO_ALT_HPI,
+	GPIO_ALT_USB_OTG,
+	GPIO_ALT_SDIO,
+	GPIO_ALT_HSMMC,
+	GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+	GPIO_ALT_HSI1,
+	GPIO_ALT_NOR,
+	GPIO_ALT_NAND,
+	GPIO_ALT_KEYPAD,
+	GPIO_ALT_VPIP,
+	GPIO_ALT_CAM,
+	GPIO_ALT_CCP1,
+	GPIO_ALT_EMMC,
+	GPIO_ALT_POP_EMMC,
+	GPIO_ALT_FUNMAX		/* Add new alt func before this */
+};
+
+/* Defines pin assignment(Software mode or Alternate mode) */
+enum gpio_mode {
+	GPIO_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_MODE_SOFTWARE,	/* Pin connected to GPIO (SW controlled) */
+	GPIO_ALTF_A,		/* Pin connected to altfunc 1 (HW periph 1) */
+	GPIO_ALTF_B,		/* Pin connected to altfunc 2 (HW periph 2) */
+	GPIO_ALTF_C,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_FIND,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_DISABLE	/* Pin connected to altfunc 3 (HW periph 3) */
+};
+
+/* Defines GPIO pin direction */
+enum gpio_direction {
+	GPIO_DIR_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_DIR_INPUT,		/* GPIO set as input */
+	GPIO_DIR_OUTPUT		/* GPIO set as output */
+};
+
+/* Interrupt trigger mode */
+enum gpio_trig {
+	GPIO_TRIG_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_TRIG_DISABLE,	/* Trigger no IT */
+	GPIO_TRIG_RISING_EDGE,	/* Trigger an IT on rising edge */
+	GPIO_TRIG_FALLING_EDGE,	/* Trigger an IT on falling edge */
+	GPIO_TRIG_BOTH_EDGES,	/* Trigger an IT on rising and falling edge */
+	GPIO_TRIG_HIGH_LEVEL,	/* Trigger an IT on high level */
+	GPIO_TRIG_LOW_LEVEL	/* Trigger an IT on low level */
+};
+
+/* Configuration parameters for one GPIO pin.*/
+struct gpio_config {
+	enum gpio_mode mode;
+	enum gpio_direction direction;
+	enum gpio_trig trig;
+	char *dev_name;		/* Who owns the gpio pin */
+};
+
+/* GPIO pin data*/
+enum gpio_data {
+	GPIO_DATA_LOW,
+	GPIO_DATA_HIGH
+};
+
+/* GPIO behaviour in sleep mode */
+enum gpio_sleep_mode {
+	GPIO_SLEEP_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT,	/* GPIO is an input with pull
+						   up/down enabled when in sleep
+						   mode. */
+	GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO	/* GPIO pin is controlled by
+						   GPIO IP. So mode, direction
+						   and data values for GPIO pin
+						   in sleep mode are determined
+						   by configuration set to GPIO
+						   pin before entering to sleep
+						   mode. */
+};
+
+/* GPIO ability to wake the system up from sleep mode.*/
+enum gpio_wake {
+	GPIO_WAKE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_WAKE_DISABLE,	/* No wake of system from sleep mode. */
+	GPIO_WAKE_LOW_LEVEL,	/* Wake the system up on a LOW level. */
+	GPIO_WAKE_HIGH_LEVEL,	/* Wake the system up on a HIGH level. */
+	GPIO_WAKE_RISING_EDGE,	/* Wake the system up on a RISING edge. */
+	GPIO_WAKE_FALLING_EDGE,	/* Wake the system up on a FALLING edge. */
+	GPIO_WAKE_BOTH_EDGES	/* Wake the system up on both RISE and FALL. */
+};
+
+/* Configuration parameters for one GPIO pin in sleep mode.*/
+struct gpio_sleep_config {
+	enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
+	enum gpio_wake wake;		/* GPIO ability to wake up system. */
+};
+
+extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
+extern int gpio_resetpinconfig(int pin_id, char *dev_name);
+extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
+extern int gpio_readpin(int pin_id, enum gpio_data *value);
+extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
+				      char *dev_name);
+extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
+				       char *dev_name);
+
+struct gpio_altfun_data {
+	u16 altfun;
+	u16 start;
+	u16 end;
+	u16 cont;
+	u8 type;
+};
+#endif
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h
new file mode 100644
index 00000000..e6a899da
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Peripheral clusters */
+
+#define U8500_PER3_BASE		0x80000000
+#define U8500_PER2_BASE		0x80110000
+#define U8500_PER1_BASE		0x80120000
+#define U8500_PER4_BASE		0x80150000
+
+#define U8500_PER6_BASE		0xa03c0000
+#define U8500_PER7_BASE		0xa03d0000
+#define U8500_PER5_BASE		0xa03e0000
+
+/* GPIO */
+
+#define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO2_BASE	(U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xE000 + 0x80)
+#define U8500_GPIO4_BASE	(U8500_PER3_BASE + 0xE000 + 0x100)
+#define U8500_GPIO5_BASE	(U8500_PER3_BASE + 0xE000 + 0x180)
+
+#define U8500_GPIO6_BASE	(U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO7_BASE	(U8500_PER2_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO8_BASE	(U8500_PER5_BASE + 0x1E000)
+
+/* Per7 */
+#define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)
+
+/* Per6 */
+#define U8500_MTU0_BASE_V1	(U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1	(U8500_PER6_BASE + 0x7000)
+#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
+
+/* Per5 */
+#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
+
+/* Per4 */
+#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
+
+/* Per3 */
+#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
+#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
+
+/* Per2 */
+#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
+
+/* Per1 */
+#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
+#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
+
+/* Last page of Boot ROM */
+#define U8500_BOOTROM_BASE      0x90000000
+#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
+#define U8500_ASIC_ID_LOC_V2    (U8500_BOOTROM_BASE + 0x1DBF4)
+
+/* AB8500 specifics */
+
+/* address bank */
+#define AB8500_REGU_CTRL2	0x0004
+#define AB8500_MISC		0x0010
+
+/* registers */
+#define AB8500_REGU_VRF1VAUX3_REGU_REG	0x040A
+#define AB8500_REGU_VRF1VAUX3_SEL_REG	0x0421
+#define AB8500_REV_REG			0x1080
+
+#define AB8500_GPIO_SEL2_REG	0x1001
+#define AB8500_GPIO_DIR2_REG	0x1011
+#define AB8500_GPIO_DIR4_REG	0x1013
+#define AB8500_GPIO_SEL4_REG	0x1003
+#define AB8500_GPIO_OUT2_REG	0x1021
+#define AB8500_GPIO_OUT4_REG	0x1023
+
+#define LDO_VAUX3_ENABLE_MASK	0x3
+#define LDO_VAUX3_ENABLE_VAL	0x1
+#define LDO_VAUX3_SEL_MASK	0xf
+#define LDO_VAUX3_SEL_2V9	0xd
+#define LDO_VAUX3_V2_SEL_MASK	0x7
+#define LDO_VAUX3_V2_SEL_2V91	0x7
+
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h
new file mode 100644
index 00000000..e7f04500
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson SA
+ *
+ * Copied from the Linux version:
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MACH_PRCMU_FW_V1_H
+#define __MACH_PRCMU_FW_V1_H
+
+#define AP_EXECUTE	2
+#define I2CREAD		1
+#define I2C_WR_OK	1
+#define I2C_RD_OK	2
+#define I2CWRITE	0
+
+#define PRCMU_BASE			U8500_PRCMU_BASE
+#define PRCMU_BASE_TCDM			U8500_PRCMU_TCDM_BASE
+#define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
+#define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
+#define PRCM_MBOX_CPU_VAL		(PRCMU_BASE + 0x0FC)
+#define PRCM_MBOX_CPU_SET		(PRCMU_BASE + 0x100)
+
+#define PRCM_ARM_IT1_CLEAR		(PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL		(PRCMU_BASE + 0x494)
+#define PRCM_TCR			(PRCMU_BASE + 0x1C8)
+#define PRCM_REQ_MB5			(PRCMU_BASE_TCDM + 0xE44)
+#define PRCM_ACK_MB5			(PRCMU_BASE_TCDM + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE		(PRCMU_BASE_TCDM + 0xFFC)
+/* Mailbox 5 Requests */
+#define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
+#define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
+#define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
+#define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
+
+/* Mailbox 5 ACKs */
+#define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
+#define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
+#define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
+
+#define LOW_POWER_WAKEUP	1
+#define EXE_WAKEUP		0
+
+#define REQ_MB5			5
+
+#define ab8500_read	prcmu_i2c_read
+#define ab8500_write	prcmu_i2c_write
+
+int prcmu_i2c_read(u8 reg, u16 slave);
+int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+
+void u8500_prcmu_enable(u32 *reg);
+void db8500_prcmu_init(void);
+
+#endif /* __MACH_PRCMU_FW_V1_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h
new file mode 100644
index 00000000..03a3cd35
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void gpio_init(void);
+int u8500_mmc_power_init(void);
+
+#endif  /* _SYS_PROTO_H_ */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h b/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h
new file mode 100644
index 00000000..16ad081b
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __U8500_H
+#define __U8500_H
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock
+						   Management Unit */
+#define CFG_SDRAMC_BASE		0x903CF000	/* SDRAMC cnf registers */
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define U8500_GPIO_0_BASE			0x8012E000
+#define U8500_GPIO_1_BASE			0x8012E080
+#define U8500_GPIO_2_BASE			0x8000E000
+#define U8500_GPIO_3_BASE			0x8000E080
+#define U8500_GPIO_4_BASE			0x8000E100
+#define U8500_GPIO_5_BASE			0x8000E180
+#define U8500_GPIO_6_BASE			0x8011E000
+#define U8500_GPIO_7_BASE			0x8011E080
+#define U8500_GPIO_8_BASE			0xA03FE000
+
+#endif	/* __U8500_H */