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| author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
| commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
| tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h | |
| download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip | |
Diffstat (limited to 'roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h')
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h b/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h new file mode 100644 index 00000000..5063e396 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _DV_AINTC_DEFS_H_ +#define _DV_AINTC_DEFS_H_ + +struct dv_aintc_regs { + unsigned int fiq0; /* 0x00 */ + unsigned int fiq1; /* 0x04 */ + unsigned int irq0; /* 0x08 */ + unsigned int irq1; /* 0x0c */ + unsigned int fiqentry; /* 0x10 */ + unsigned int irqentry; /* 0x14 */ + unsigned int eint0; /* 0x18 */ + unsigned int eint1; /* 0x1c */ + unsigned int intctl; /* 0x20 */ + unsigned int eabase; /* 0x24 */ + unsigned char rsvd0[8]; /* 0x28 */ + unsigned int intpri0; /* 0x30 */ + unsigned int intpri1; /* 0x34 */ + unsigned int intpri2; /* 0x38 */ + unsigned int intpri3; /* 0x3c */ + unsigned int intpri4; /* 0x40 */ + unsigned int intpri5; /* 0x44 */ + unsigned int intpri6; /* 0x48 */ + unsigned int intpri7; /* 0x4c */ +}; + +#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) + +#define DV_AINTC_INTCTL_IDMODE (1 << 2) + +#endif /* _DV_AINTC_DEFS_H_ */ |