diff options
author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
---|---|---|
committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c')
-rw-r--r-- | roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c b/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 00000000..e320c011 --- /dev/null +++ b/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} |