diff options
author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
---|---|---|
committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c')
-rw-r--r-- | roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c b/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c new file mode 100644 index 00000000..3beb0ed9 --- /dev/null +++ b/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -0,0 +1,27 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sysmap.h> + +#define EN_MASK 0x08000000 /* Enable timer */ +#define SRSTEN_MASK 0x04000000 /* Enable soft reset */ +#define CLKS_SHIFT 20 /* Clock period shift */ +#define LD_SHIFT 0 /* Reload value shift */ + +void reset_cpu(ulong ignored) +{ + /* + * Set WD enable, RST enable, + * 3.9 msec clock period (8), reload value (8*3.9ms) + */ + u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); + writel(reg, SECWD2_BASE_ADDR); + + while (1) + ; /* loop forever till reset */ +} |