Initial import of qemu-2.4.1HEADmaster

1 files changed, 37 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c b/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c
new file mode 100644
index 00000000..bb5ffd29
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -0,0 +1,37 @@
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}