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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h | |
download | qemu-master.tar.gz qemu-master.tar.bz2 qemu-master.zip |
Diffstat (limited to 'roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h')
-rw-r--r-- | roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h b/roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h new file mode 100644 index 00000000..8ac179de --- /dev/null +++ b/roms/ipxe/src/drivers/net/igbvf/igbvf_osdep.h @@ -0,0 +1,118 @@ +/******************************************************************************* + + Intel(R) 82576 Virtual Function Linux driver + Copyright(c) 1999 - 2008 Intel Corporation. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, + version 2, as published by the Free Software Foundation. + + This program is distributed in the hope it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + + The full GNU General Public License is included in this distribution in + the file called "COPYING". + + Contact Information: + Linux NICS <linux.nics@intel.com> + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ + +FILE_LICENCE ( GPL2_ONLY ); + +/* glue for the OS-dependent part of igbvf + * includes register access macros + */ + +#ifndef _IGBVF_OSDEP_H_ +#define _IGBVF_OSDEP_H_ + +#define u8 unsigned char +#define bool boolean_t +#define dma_addr_t unsigned long +#define __le16 uint16_t +#define __le32 uint32_t +#define __le64 uint64_t + +#define __iomem +#define __devinit +#define ____cacheline_aligned_in_smp + +#define msleep(x) mdelay(x) + +#define ETH_FCS_LEN 4 + +typedef int spinlock_t; +typedef enum { + false = 0, + true = 1 +} boolean_t; + +#define usec_delay(x) udelay(x) +#define msec_delay(x) mdelay(x) +#define msec_delay_irq(x) mdelay(x) + +#define PCI_COMMAND_REGISTER PCI_COMMAND +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE +#define ETH_ADDR_LEN ETH_ALEN + + +#define DEBUGOUT(S) if (0) { printf(S); } +#define DEBUGOUT1(S, A...) if (0) { printf(S, A); } + +#define DEBUGFUNC(F) DEBUGOUT(F "\n") +#define DEBUGOUT2 DEBUGOUT1 +#define DEBUGOUT3 DEBUGOUT2 +#define DEBUGOUT7 DEBUGOUT3 + +#define E1000_WRITE_REG(a, reg, value) do { \ + writel((value), ((a)->hw_addr + reg)); } while (0) + +#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg)) + +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \ + writel((value), ((a)->hw_addr + reg + ((offset) << 2))); } while (0) + +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ + readl((a)->hw_addr + reg + ((offset) << 2))) + +#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY +#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY + +#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ + writew((value), ((a)->hw_addr + reg + ((offset) << 1)))) + +#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ + readw((a)->hw_addr + reg + ((offset) << 1))) + +#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ + writeb((value), ((a)->hw_addr + reg + (offset)))) + +#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ + readb((a)->hw_addr + reg + (offset))) + +#define E1000_WRITE_REG_IO(a, reg, offset) do { \ + outl(reg, ((a)->io_base)); \ + outl(offset, ((a)->io_base + 4)); } while(0) + +#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) + +#define E1000_WRITE_FLASH_REG(a, reg, value) ( \ + writel((value), ((a)->flash_address + reg))) + +#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \ + writew((value), ((a)->flash_address + reg))) + +#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg)) + +#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg)) + +#endif /* _IGBVF_OSDEP_H_ */ |