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| author | fishsoupisgood <github@madingley.org> | 2019-05-27 02:41:51 +0100 | 
|---|---|---|
| committer | fishsoupisgood <github@madingley.org> | 2019-05-27 02:41:51 +0100 | 
| commit | 333b605b2afd472b823aeda0adf0e8b1ea9843c0 (patch) | |
| tree | bc8f581317897e2e53f278f1716b4471fcdccd4f /tests/t_st6 | |
| download | asl-master.tar.gz asl-master.tar.bz2 asl-master.zip  | |
Diffstat (limited to 'tests/t_st6')
| -rw-r--r-- | tests/t_st6/asflags | 0 | ||||
| -rwxr-xr-x | tests/t_st6/t_st6.asm | 82 | ||||
| -rw-r--r-- | tests/t_st6/t_st6.doc | 5 | ||||
| -rwxr-xr-x | tests/t_st6/t_st6.ori | bin | 0 -> 102 bytes | 
4 files changed, 87 insertions, 0 deletions
diff --git a/tests/t_st6/asflags b/tests/t_st6/asflags new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/tests/t_st6/asflags diff --git a/tests/t_st6/t_st6.asm b/tests/t_st6/t_st6.asm new file mode 100755 index 0000000..7cbdc2b --- /dev/null +++ b/tests/t_st6/t_st6.asm @@ -0,0 +1,82 @@ +        cpu     st6225 + +        nop +        ret +        reti +        stop +        wait + +        jrz     pc +        jrnz    pc+1 +        jrc     pc+2 +        jrnc    pc+3 + +        ld      a,v +        ld      a,w +        ld      a,x +        ld      a,y +        ld      a,12h +        ld      a,(x) +        ld      a,(y) +        ld      v,a +        ld      12h,a +        ld      (x),a +        ld      (y),a + +        ldi     a,12h +        ldi     v,12h +        ldi     12h,12h + +        jp      123h +        call    123h + +        add     a,v +        add     a,12h +        add     a,(x) +        add     a,(y) + +        and     a,v +        and     a,12h +        and     a,(x) +        and     a,(y) + +        cp     a,v +        cp     a,12h +        cp     a,(x) +        cp     a,(y) + +        sub     a,v +        sub     a,12h +        sub     a,(x) +        sub     a,(y) + +        addi    a,12h +        andi    a,12h +        cpi     a,12h +        subi    a,12h + +        clr     a +        clr     v +        clr     12h + +        com     a +        rlc     a +        sla     a + +        inc     a +        inc     v +        inc     12h +        inc     (x) +        inc     (y) + +        dec     a +        dec     v +        dec     12h +        dec     (x) +        dec     (y) + +        set     3,v +        res     5,12h + +        jrs     3,v,pc +        jrr     5,12h,pc+1 diff --git a/tests/t_st6/t_st6.doc b/tests/t_st6/t_st6.doc new file mode 100644 index 0000000..311bc51 --- /dev/null +++ b/tests/t_st6/t_st6.doc @@ -0,0 +1,5 @@ ++------------------------- Test Application ST6 -----------------------------+ +|                                                                            | +|          This is a (synthetic) test of the ST6's instruction set           | +|                                                                            | ++----------------------------------------------------------------------------+ diff --git a/tests/t_st6/t_st6.ori b/tests/t_st6/t_st6.ori Binary files differnew file mode 100755 index 0000000..c7e305a --- /dev/null +++ b/tests/t_st6/t_st6.ori  | 
