switch to 10MHz system clock

2 files changed, 148 insertions, 61 deletions

diff --git a/app/main.c b/app/main.c
index 707d230..4793f78 100644
--- a/app/main.c
+++ b/app/main.c
@@ -15,6 +15,8 @@ void exti15_10_isr (void)
 }
 #endif
 
+
+
 static void cmd_dispatch (void)
 {
   uint8_t c;
@@ -45,67 +47,8 @@ static void cmd_dispatch (void)
   }
 }
 
-static const clock_scale_t hse_10mhz_3v3_168 = {
-  /* 168MHz */
-  .pllm = 10,
-  .plln = 336,
-  .pllp = 2,
-  .pllq = 7,
-  .hpre = RCC_CFGR_HPRE_DIV_NONE,
-  .ppre1 = RCC_CFGR_PPRE_DIV_4,
-  .ppre2 = RCC_CFGR_PPRE_DIV_2,
-  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
-  FLASH_ACR_LATENCY_5WS,
-  .apb1_frequency = 42000000,
-  .apb2_frequency = 84000000,
-};
-
-static const clock_scale_t hse_10mhz_3v3_120 = {
-  /* 120 */
-  .pllm = 10,
-  .plln = 240,
-  .pllp = 2,
-  .pllq = 5,
-  .hpre = RCC_CFGR_HPRE_DIV_NONE,
-  .ppre1 = RCC_CFGR_PPRE_DIV_4,
-  .ppre2 = RCC_CFGR_PPRE_DIV_2,
-  .power_save = 1,
-  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
-  FLASH_ACR_LATENCY_3WS,
-  .apb1_frequency = 30000000,
-  .apb2_frequency = 60000000,
-};
-
-static const clock_scale_t hse_10mhz_3v3_84 = {
-  .pllm = 10,
-  .plln = 336,
-  .pllp = 4,
-  .pllq = 7,
-  .hpre = RCC_CFGR_HPRE_DIV_NONE,
-  .ppre1 = RCC_CFGR_PPRE_DIV_2,
-  .ppre2 = RCC_CFGR_PPRE_DIV_NONE,
-  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
-  FLASH_ACR_LATENCY_2WS,
-  .apb1_frequency = 42000000,
-  .apb2_frequency = 84000000,
-};
-
-
-static const clock_scale_t hse_10mhz_3v3_48 = {
-  .pllm = 10,
-  .plln = 96,
-  .pllp = 2,
-  .pllq = 2,
-  .hpre = RCC_CFGR_HPRE_DIV_NONE,
-  .ppre1 = RCC_CFGR_PPRE_DIV_4,
-  .ppre2 = RCC_CFGR_PPRE_DIV_2,
-  .power_save = 1,
-  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
-  FLASH_ACR_LATENCY_3WS,
-  .apb1_frequency = 12000000,
-  .apb2_frequency = 24000000,
-};
 
+#if 0
 static void pd_port (uint32_t p)
 {
   unsigned c;
@@ -177,13 +120,156 @@ static void pd(void)
 
   for (;;);
 }
+#endif
+
+
+static const clock_scale_t hse_10mhz_3v3_168 = {
+  /* 168MHz */
+  .pllm = 10,
+  .plln = 336,
+  .pllp = 2,
+  .pllq = 7,
+  .hpre = RCC_CFGR_HPRE_DIV_NONE,
+  .ppre1 = RCC_CFGR_PPRE_DIV_4,
+  .ppre2 = RCC_CFGR_PPRE_DIV_2,
+  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
+  FLASH_ACR_LATENCY_5WS,
+  .apb1_frequency = 42000000,
+  .apb2_frequency = 84000000,
+};
+
+static const clock_scale_t hse_10mhz_3v3_120 = {
+  /* 120 */
+  .pllm = 10,
+  .plln = 240,
+  .pllp = 2,
+  .pllq = 5,
+  .hpre = RCC_CFGR_HPRE_DIV_NONE,
+  .ppre1 = RCC_CFGR_PPRE_DIV_4,
+  .ppre2 = RCC_CFGR_PPRE_DIV_2,
+  .power_save = 1,
+  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
+  FLASH_ACR_LATENCY_3WS,
+  .apb1_frequency = 30000000,
+  .apb2_frequency = 60000000,
+};
+
+static const clock_scale_t hse_10mhz_3v3_84 = {
+  .pllm = 10,
+  .plln = 336,
+  .pllp = 4,
+  .pllq = 7,
+  .hpre = RCC_CFGR_HPRE_DIV_NONE,
+  .ppre1 = RCC_CFGR_PPRE_DIV_2,
+  .ppre2 = RCC_CFGR_PPRE_DIV_NONE,
+  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
+  FLASH_ACR_LATENCY_2WS,
+  .apb1_frequency = 42000000,
+  .apb2_frequency = 84000000,
+};
+
+
+static const clock_scale_t hse_10mhz_3v3_48 = {
+  .pllm = 10,
+  .plln = 96,
+  .pllp = 2,
+  .pllq = 2,
+  .hpre = RCC_CFGR_HPRE_DIV_NONE,
+  .ppre1 = RCC_CFGR_PPRE_DIV_4,
+  .ppre2 = RCC_CFGR_PPRE_DIV_2,
+  .power_save = 1,
+  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
+  FLASH_ACR_LATENCY_3WS,
+  .apb1_frequency = 12000000,
+  .apb2_frequency = 24000000,
+};
+
+static const clock_scale_t hse_10mhz_3v3_10 = {
+  /* 10 */
+  .pllm = 10,
+  .plln = 336,
+  .pllp = 2,
+  .pllq = 7,
+  .hpre = RCC_CFGR_HPRE_DIV_NONE,
+  .ppre1 = RCC_CFGR_PPRE_DIV_NONE,
+  .ppre2 = RCC_CFGR_PPRE_DIV_NONE,
+  .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_0WS,
+//  .ahb_frequency  = 10000000,
+  .apb1_frequency = 10000000,
+  .apb2_frequency = 10000000,
+};
+
+/*
+ * Erugh the STM32F4's PLL is shite, we need 
+ * to drive the entire clock tree from the 10MHz 
+ * input, we use the PLL only to drive the 48MHz 
+ * clock tree. 
+ *
+ * So PTP, AHB, APB1, APB2 all are directly from 
+ * the HSE input 
+ */
+
+
+void rcc_clock_setup_hse_3v3_no_pll(const clock_scale_t *clock)
+{
+        /* Enable internal high-speed oscillator. */
+        rcc_osc_on(HSI);
+        rcc_wait_for_osc_ready(HSI);
+
+        /* Select HSI as SYSCLK source. */
+        rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
+
+        /* Enable external high-speed oscillator 8MHz. */
+        rcc_osc_on(HSE);
+        rcc_wait_for_osc_ready(HSE);
+
+        /* Enable/disable high performance mode */
+        if (!clock->power_save) {
+                pwr_set_vos_scale(SCALE1);
+        } else {
+                pwr_set_vos_scale(SCALE2);
+        }
+
+        /*
+         * Set prescalers for AHB, ADC, ABP1, ABP2.
+         * Do this before touching the PLL (TODO: why?).
+         */
+        rcc_set_hpre(clock->hpre);
+        rcc_set_ppre1(clock->ppre1);
+        rcc_set_ppre2(clock->ppre2);
+
+        rcc_set_main_pll_hse(clock->pllm, clock->plln,
+                        clock->pllp, clock->pllq);
+
+        /* Enable PLL oscillator and wait for it to stabilize. */
+        rcc_osc_on(PLL);
+        rcc_wait_for_osc_ready(PLL);
+
+        /* Configure flash settings. */
+        flash_set_ws(clock->flash_config);
+
+        /* Select PLL as SYSCLK source. */
+        rcc_set_sysclk_source(RCC_CFGR_SW_HSE);
+
+        /* Wait for PLL clock to be selected. */
+        rcc_wait_for_sysclk_status(HSE);
+
+        /* Set the peripheral clock frequencies used. */
+        rcc_apb1_frequency = clock->apb1_frequency;
+        rcc_apb2_frequency = clock->apb2_frequency;
+
+        /* Disable internal high-speed oscillator. */
+        rcc_osc_off(HSI);
+}
+
 
 static void
 board_setup (void)
 {
   rcc_osc_bypass_enable (HSE);
   RCC_SSCGR = 0;
-  rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168);
+//  rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168);
+  rcc_clock_setup_hse_3v3_no_pll (&hse_10mhz_3v3_10);
 
   rcc_periph_clock_enable (RCC_SYSCFG);
   rcc_periph_clock_enable (RCC_GPIOA);
diff --git a/lwip/lwip-local/port/stm32f4x7/arch/cc.h b/lwip/lwip-local/port/stm32f4x7/arch/cc.h
index e0f8ab6..aa0ec4c 100644
--- a/lwip/lwip-local/port/stm32f4x7/arch/cc.h
+++ b/lwip/lwip-local/port/stm32f4x7/arch/cc.h
@@ -32,6 +32,7 @@
 #ifndef __CC_H__

 #define __CC_H__

 

+#undef BYTE_ORDER

 #include "cpu.h"

 

 typedef unsigned   char    u8_t;