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	Commit message (Expand)	Author	Age	Files	Lines
*	tools: add Broadcom cable modem firmware image creator	Florian Fainelli	2013-06-06	4	-0/+513
*	Revert "[tools] mklibs: upgrade to 0.1.37"	Felix Fietkau	2013-06-05	11	-23/+23
*	mpfr: upgrade to 3.1.2	Luka Perkov	2013-06-03	1	-2/+2
*	gmp: upgrade to version 5.1.2	Luka Perkov	2013-06-03	1	-2/+2
*	mklibs: upgrade to 0.1.37	Luka Perkov	2013-06-03	11	-23/+23
*	firmware-utils/mkcameofw: allow to use combined kernel image	Gabor Juhos	2013-05-08	1	-28/+56
*	tools/mkimage: unbreak non-linux build again	Felix Fietkau	2013-05-06	1	-0/+35
*	mkimage: update to 2013.04	Luka Perkov	2013-05-05	6	-24/+96
*	tools/mtools: disable iconv support, it breaks on some systems	Felix Fietkau	2013-05-02	1	-0/+3
*	firmware-utils/mktplinkfw: add description for -W option into usage output	Gabor Juhos	2013-04-30	1	-0/+1
*	firmware-utils/mktplinkfw: add support for the TL-WR720N v3 board	Gabor Juhos	2013-04-26	1	-0/+6
*	Add Netgear WNCE2001 (OF version)	John Crispin	2013-04-09	1	-2/+37
*	tools/upx: use HOSTCXX to fix build errors on mac os x	Felix Fietkau	2013-03-22	1	-1/+2
*	firmware-utils/mktplinkfw: Add support for MR3420v2	Gabor Juhos	2013-03-11	1	-0/+6
*	mkimage: unbreak build on non-linux systems	Felix Fietkau	2013-03-09	1	-0/+31
*	mkimage: upgrade to version 2013.01.01	Luka Perkov	2013-03-08	5	-19/+18
*	build: BSD compile fixes	Felix Fietkau	2013-03-07	10	-9/+130
*	b43-tools: fix compile error: undefined reference to `yydebug'	Hauke Mehrtens	2013-02-28	1	-0/+27
*	mpfr: upgrade to 3.1.1	Luka Perkov	2013-02-28	4	-1974/+25
*	bison: upgrade to version 2.7	Luka Perkov	2013-02-28	4	-26/+27
*	cmake: upgrade to version 2.8.10.2	Luka Perkov	2013-02-28	1	-3/+3
*	e2fsprogs: upgrade to version 1.42.7	Luka Perkov	2013-02-28	1	-3/+3
*	flex: upgrade to version 2.5.37	Luka Perkov	2013-02-28	1	-3/+3
*	gmp: upgrade to version 5.1.1	Luka Perkov	2013-02-28	3	-216/+5
*	sed: upgrade to version 4.2.2	Luka Perkov	2013-02-28	1	-3/+3
*	ccache: upgrade to version 3.1.9	Luka Perkov	2013-02-27	1	-3/+3
*	mklibs: upgrade to 0.1.35	Luka Perkov	2013-02-26	3	-3/+14
*	firmware-utils/mktplinkfw: add support for the TL-WA830RE v1/v2 boards	Gabor Juhos	2013-02-25	1	-0/+12
*	firmware-utils/mktplinkfw: add support for the TL-WDR4900 v1	Gabor Juhos	2013-02-13	1	-0/+12
*	firmware-utils/mktplinkfw: add TP-LINK TL-WR743ND v2 support	Gabor Juhos	2013-02-02	1	-0/+6
*	adds support for Edimax BR-6524N	John Crispin	2013-01-06	2	-0/+2
*	tools/ipkg-utils: remove some unnecessary field checks	Felix Fietkau	2012-12-22	1	-0/+36
*	firmware-utils/mktplinkfw: add support for the TL-MR3220 v2	Gabor Juhos	2012-12-19	1	-0/+6
*	tools: add a symlink for gnu awk to fix kernel build errors on some platforms	Felix Fietkau	2012-12-17	1	-1/+2
*	firmware-utils/mkfwimage2: allow to use numbers in partition names	Gabor Juhos	2012-12-17	1	-1/+1
*	firmware-utils/mktplinkfw: add support for TP-LINK WA801NDv1	Gabor Juhos	2012-12-07	1	-0/+6
*	b43-tools: update to version 017, which contains the patch.	Hauke Mehrtens	2012-12-07	2	-25/+3
*	tools: e2fsprogs: delete doc/ directory after unpacking to ensure that makein...	Jo-Philipp Wich	2012-12-02	1	-0/+5
*	tools/sstrip: remove redundant -I flag that breaks build on some x86_64 linux...	Felix Fietkau	2012-12-02	1	-1/+1
*	b43-tools: pack the lcn firmware into the brcmsmac firmware package.	Hauke Mehrtens	2012-12-02	1	-0/+22
*	sstrip: remove a redundant copy of elf.h	Felix Fietkau	2012-12-02	2	-2446/+1
*	ipkg-utils: Force gnu format for tar (#12496)	Vasilis Tsiligiannis	2012-11-19	1	-0/+27
*	firmware-utils/mktplinkfw: add support for TL-WA7510N	Gabor Juhos	2012-11-13	1	-0/+6
*	rename patch-cmdline and add code for patching DTB files into kernel images	John Crispin	2012-11-02	4	-3/+107
*	b43-tools: get rid of the libfl dependency to fix build errors on mac os x	Felix Fietkau	2012-10-25	2	-0/+15
*	b43-tools: fix md5sum	Hauke Mehrtens	2012-10-25	1	-1/+1
*	firmware-utils: new tool for fixing U-Media firmware headers	Gabor Juhos	2012-10-18	2	-0/+355
*	tools/firmware-utils: add seama tool	Gabor Juhos	2012-10-18	3	-0/+638
*	mac80211: brcmsmac: use firmware extracted from proprietary driver	Hauke Mehrtens	2012-10-08	1	-1/+1
*	tools: add b43-tools	Hauke Mehrtens	2012-10-08	4	-0/+192

• [next]

generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 00:56:50 +0000

```
yosys -- Yosys Open SYnthesis Suite

Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>

Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
```


yosys – Yosys Open SYnthesis Suite
===================================

This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).


Web Site and Other Resources
============================

More information and documentation can be found on the Yosys web site:
- http://www.clifford.at/yosys/

The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
- http://www.clifford.at/yosys/documentation.html

The file `CodingReadme` in this directory contains additional information
for people interested in using the Yosys C++ APIs.

Users interested in formal verification might want to use the formal verification
front-end for Yosys, SymbiYosys:
- https://symbiyosys.readthedocs.io/en/latest/
- https://github.com/YosysHQ/SymbiYosys


Setup
======

You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.

For example on Ubuntu Linux 16.04 LTS the following commands will install all
prerequisites for building yosys:

	$ sudo apt-get install build-essential clang bison flex \
		libreadline-dev gawk tcl-dev libffi-dev git \
		graphviz xdot pkg-config python3 libboost-system-dev \
		libboost-python-dev libboost-filesystem-dev zlib1g-dev

Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):

	$ brew tap Homebrew/bundle && brew bundle

or MacPorts:

	$ sudo port install bison flex readline gawk libffi \
		git graphviz pkgconfig python36 boost zlib tcl

On FreeBSD use the following command to install all prerequisites:

	# pkg install bison flex readline gawk libffi\
		git graphviz pkgconf python3 python36 tcl-wrapper boost-libs

On FreeBSD system use gmake instead of make. To run tests use:
    % MAKE=gmake CC=cc gmake test

For Cygwin use the following command to install all prerequisites, or select these additional packages:

	setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel

There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
as a source distribution for Visual Studio. Visit the Yosys download page for
more information: http://www.clifford.at/yosys/download.html

To configure the build system to use a specific compiler, use one of

	$ make config-clang
	$ make config-gcc

For other compilers and build configurations it might be
necessary to make some changes to the config section of the
Makefile.

	$ vi Makefile            # ..or..
	$ vi Makefile.conf

To build Yosys simply type 'make' in this directory.

	$ make
	$ sudo make install

Note that this also downloads, builds and installs ABC (using yosys-abc
as executable name).

Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:

	$ make test

Getting Started
===============

Yosys can be used with the interactive command shell, with
synthesis scripts or with command line arguments. Let's perform
a simple synthesis job using the interactive command shell:

	$ ./yosys
	yosys>

the command ``help`` can be used to print a list of all available
commands and ``help <command>`` to print details on the specified command:

	yosys> help help

reading and elaborating the design using the Verilog frontend:

	yosys> read -sv tests/simple/fiedler-cooley.v
	yosys> hierarchy -top up3down5

writing the design to the console in Yosys's internal format:

	yosys> write_ilang

convert processes (``always`` blocks) to netlist elements and perform
some simple optimizations:

	yosys> proc; opt

display design netlist using ``xdot``:

	yosys> show

the same thing using ``gv`` as postscript viewer:

	yosys> show -format ps -viewer gv

translating netlist to gate logic and perform some simple optimizations:

	yosys> techmap; opt

write design netlist to a new Verilog file:

	yosys> write_verilog synth.v

or using a simple synthesis script:

	$ cat synth.ys
	read -sv tests/simple/fiedler-cooley.v
	hierarchy -top up3down5
	proc; opt; techmap; opt
	write_verilog synth.v

	$ ./yosys synth.ys

If ABC is enabled in the Yosys build configuration and a cell library is given
in the liberty file ``mycells.lib``, the following synthesis script will
synthesize for the given cell library:

	# read design
	read -sv tests/simple/fiedler-cooley.v
	hierarchy -top up3down5

	# the high-level stuff
	proc; fsm; opt; memory; opt

	# mapping to internal cell library
	techmap; opt

	# mapping flip-flops to mycells.lib
	dfflibmap -liberty mycells.lib

	# mapping logic to mycells.lib
	abc -liberty mycells.lib

	# cleanup
	clean

If you do not have a liberty file but want to test this synthesis script,
you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
as simple example.

Liberty file downloads for and information about free and open ASIC standard
cell libraries can be found here:

- http://www.vlsitechnology.org/html/libraries.html
- http://www.vlsitechnology.org/synopsys/vsclib013.lib

The command ``synth`` provides a good default synthesis script (see
``help synth``):

	read -sv tests/simple/fiedler-cooley.v
	synth -top up3down5

	# mapping to target cells
	dfflibmap -liberty mycells.lib
	abc -liberty mycells.lib
	clean

The command ``prep`` provides a good default word-level synthesis script, as
used in SMT-based formal verification.


Unsupported Verilog-2005 Features
=================================

The following Verilog-2005 features are not supported by
Yosys and there are currently no plans to add support
for them:

- Non-synthesizable language features as defined in
	IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002

- The ``tri``, ``triand`` and ``trior`` net types

- The ``config`` and ``disable`` keywords and library map files


Verilog Attributes and non-standard features
============================================

- The ``full_case`` attribute on case statements is supported
  (also the non-standard ``// synopsys full_case`` directive)

- The ``parallel_case`` attribute on case statements is supported
  (also the non-standard ``// synopsys parallel_case`` directive)

- The ``// synopsys translate_off`` and ``// synopsys translate_on``
  directives are also supported (but the use of ``` `ifdef .. `endif ```
  is strongly recommended instead).

- The ``nomem2reg`` attribute on modules or arrays prohibits the
  automatic early conversion of arrays to separate registers. This
  is potentially dangerous. Usually the front-end has good reasons
  for converting an array to a list of registers. Prohibiting this
  step will likely result in incorrect synthesis results.

- The ``mem2reg`` attribute on modules or arrays forces the early
  conversion of arrays to separate registers.

- The ``nomeminit`` attribute on modules or arrays prohibits the
  creation of initialized memories. This effectively puts ``mem2reg``
  on all memories that are written to in an ``initial`` block and
  are not ROMs.

- The ``nolatches`` attribute on modules or always-blocks
  prohibits the generation of logic-loops for latches. Instead
  all not explicitly assigned values default to x-bits. This does
  not affect clocked storage elements such as flip-flops.

- The ``nosync`` attribute on registers prohibits the generation of a
  storage element. The register itself will always have all bits set
  to 'x' (undefined). The variable may only be used as blocking assigned
  temporary variable within an always block. This is mostly used internally
  by Yosys to synthesize Verilog functions and access arrays.

- The ``onehot`` attribute on wires mark them as one-hot state register. This
  is used for example for memory port sharing and set by the fsm_map pass.