diff options
Diffstat (limited to 'target/linux/octeontx/patches-4.14/0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch')
| -rw-r--r-- | target/linux/octeontx/patches-4.14/0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/target/linux/octeontx/patches-4.14/0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch b/target/linux/octeontx/patches-4.14/0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch new file mode 100644 index 0000000000..db57f6dcca --- /dev/null +++ b/target/linux/octeontx/patches-4.14/0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch @@ -0,0 +1,117 @@ +From b1e7791e688620c9bb8476ac2d0bc99abeb7f825 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Fri, 29 Dec 2017 16:48:04 -0800 +Subject: [PATCH] net: thunderx: workaround BGX TX Underflow issue + +While it is not yet understood why a TX underflow can easily occur +for SGMII interfaces resulting in a TX wedge. It has been found that +disabling/re-enabling the LMAC resolves the issue. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 54 +++++++++++++++++++++++ + drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++ + 2 files changed, 63 insertions(+) + +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +index 805c02a..0690966 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +@@ -1344,6 +1344,54 @@ static int bgx_init_phy(struct bgx *bgx) + return bgx_init_of_phy(bgx); + } + ++static irqreturn_t bgx_intr_handler(int irq, void *data) ++{ ++ struct bgx *bgx = (struct bgx *)data; ++ struct device *dev = &bgx->pdev->dev; ++ u64 status, val; ++ int lmac; ++ ++ for (lmac = 0; lmac < bgx->lmac_count; lmac++) { ++ status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT); ++ if (status & GMI_TXX_INT_UNDFLW) { ++ dev_err(dev, "BGX%d lmac%d UNDFLW\n", bgx->bgx_id, ++ lmac); ++ val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG); ++ val &= ~CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ val |= CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ } ++ /* clear interrupts */ ++ bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int bgx_register_intr(struct pci_dev *pdev) ++{ ++ struct bgx *bgx = pci_get_drvdata(pdev); ++ struct device *dev = &pdev->dev; ++ int num_vec, ret; ++ char irq_name[32]; ++ ++ /* Enable MSI-X */ ++ num_vec = pci_msix_vec_count(pdev); ++ ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX); ++ if (ret < 0) { ++ dev_err(dev, "Req for #%d msix vectors failed\n", num_vec); ++ return 1; ++ } ++ sprintf(irq_name, "BGX%d", bgx->bgx_id); ++ ret = request_irq(pci_irq_vector(pdev, GMPX_GMI_TX_INT), ++ bgx_intr_handler, 0, irq_name, bgx); ++ if (ret) ++ return 1; ++ ++ return 0; ++} ++ + static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + { + int err; +@@ -1414,6 +1462,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + xcv_init_hw(bgx->phy_mode); + bgx_init_hw(bgx); + ++ bgx_register_intr(pdev); ++ + /* Enable all LMACs */ + for (lmac = 0; lmac < bgx->lmac_count; lmac++) { + err = bgx_lmac_enable(bgx, lmac); +@@ -1424,6 +1474,10 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + bgx_lmac_disable(bgx, --lmac); + goto err_enable; + } ++ ++ /* enable TX FIFO Underflow interrupt */ ++ bgx_reg_modify(bgx, lmac, BGX_GMP_GMI_TXX_INT_ENA_W1S, ++ GMI_TXX_INT_UNDFLW); + } + + return 0; +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +index 2bba9d1..be9148f9 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +@@ -179,6 +179,15 @@ + #define BGX_GMP_GMI_TXX_BURST 0x38228 + #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 + #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 ++#define BGX_GMP_GMI_TXX_INT 0x38500 ++#define BGX_GMP_GMI_TXX_INT_W1S 0x38508 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518 ++#define GMI_TXX_INT_PTP_LOST BIT_ULL(4) ++#define GMI_TXX_INT_LATE_COL BIT_ULL(3) ++#define GMI_TXX_INT_XSDEF BIT_ULL(2) ++#define GMI_TXX_INT_XSCOL BIT_ULL(1) ++#define GMI_TXX_INT_UNDFLW BIT_ULL(0) + + #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ + #define BGX_MSIX_VEC_0_29_CTL 0x400008 +-- +2.7.4 + |