diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch')
-rw-r--r-- | target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch b/target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch new file mode 100644 index 0000000000..efface684d --- /dev/null +++ b/target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch @@ -0,0 +1,221 @@ +From 141fc778365ac0f1584ade0fd419af871e681646 Mon Sep 17 00:00:00 2001 +From: Claudiu Manoil <claudiu.manoil@nxp.com> +Date: Mon, 12 Aug 2019 20:26:42 +0300 +Subject: [PATCH] enetc: Make mdio accessors more generic + +Refactoring needed to support multiple MDIO buses. +'mdio_base' - MDIO registers base address - is being parameterized. +The MDIO accessors are made more generic to be able to work with +different MDIO register bases. +Some includes get cleaned up in the process. + +Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> +--- + drivers/net/ethernet/freescale/enetc/enetc_hw.h | 1 + + drivers/net/ethernet/freescale/enetc/enetc_mdio.c | 60 +++++++++++++--------- + drivers/net/ethernet/freescale/enetc/enetc_mdio.h | 2 +- + .../net/ethernet/freescale/enetc/enetc_pci_mdio.c | 2 + + 4 files changed, 39 insertions(+), 26 deletions(-) + +--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h ++++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h +@@ -198,6 +198,7 @@ enum enetc_bdr_type {TX, RX}; + #define ENETC_PFPMR 0x1900 + #define ENETC_PFPMR_PMACE BIT(1) + #define ENETC_PFPMR_MWLM BIT(0) ++#define ENETC_EMDIO_BASE 0x1c00 + #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10) + #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10) + #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10) +--- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c ++++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c +@@ -6,19 +6,30 @@ + #include <linux/iopoll.h> + #include <linux/of.h> + ++#include "enetc_pf.h" + #include "enetc_mdio.h" + +-#define ENETC_MDIO_REG_OFFSET 0x1c00 + #define ENETC_MDIO_CFG 0x0 /* MDIO configuration and status */ + #define ENETC_MDIO_CTL 0x4 /* MDIO control */ + #define ENETC_MDIO_DATA 0x8 /* MDIO data */ + #define ENETC_MDIO_ADDR 0xc /* MDIO address */ + +-#define enetc_mdio_rd(hw, off) \ +- enetc_port_rd(hw, ENETC_##off + ENETC_MDIO_REG_OFFSET) +-#define enetc_mdio_wr(hw, off, val) \ +- enetc_port_wr(hw, ENETC_##off + ENETC_MDIO_REG_OFFSET, val) +-#define enetc_mdio_rd_reg(off) enetc_mdio_rd(hw, off) ++static inline u32 _enetc_mdio_rd(struct enetc_mdio_priv *mdio_priv, int off) ++{ ++ return enetc_port_rd(mdio_priv->hw, mdio_priv->mdio_base + off); ++} ++ ++static inline void _enetc_mdio_wr(struct enetc_mdio_priv *mdio_priv, int off, ++ u32 val) ++{ ++ enetc_port_wr(mdio_priv->hw, mdio_priv->mdio_base + off, val); ++} ++ ++#define enetc_mdio_rd(mdio_priv, off) \ ++ _enetc_mdio_rd(mdio_priv, ENETC_##off) ++#define enetc_mdio_wr(mdio_priv, off, val) \ ++ _enetc_mdio_wr(mdio_priv, ENETC_##off, val) ++#define enetc_mdio_rd_reg(off) enetc_mdio_rd(mdio_priv, off) + + #define ENETC_MDC_DIV 258 + +@@ -35,7 +46,7 @@ + #define MDIO_DATA(x) ((x) & 0xffff) + + #define TIMEOUT 1000 +-static int enetc_mdio_wait_complete(struct enetc_hw *hw) ++static int enetc_mdio_wait_complete(struct enetc_mdio_priv *mdio_priv) + { + u32 val; + +@@ -46,7 +57,6 @@ static int enetc_mdio_wait_complete(stru + int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value) + { + struct enetc_mdio_priv *mdio_priv = bus->priv; +- struct enetc_hw *hw = mdio_priv->hw; + u32 mdio_ctl, mdio_cfg; + u16 dev_addr; + int ret; +@@ -61,29 +71,29 @@ int enetc_mdio_write(struct mii_bus *bus + mdio_cfg &= ~MDIO_CFG_ENC45; + } + +- enetc_mdio_wr(hw, MDIO_CFG, mdio_cfg); ++ enetc_mdio_wr(mdio_priv, MDIO_CFG, mdio_cfg); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + + /* set port and dev addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); +- enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl); ++ enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl); + + /* set the register address */ + if (regnum & MII_ADDR_C45) { +- enetc_mdio_wr(hw, MDIO_ADDR, regnum & 0xffff); ++ enetc_mdio_wr(mdio_priv, MDIO_ADDR, regnum & 0xffff); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + } + + /* write the value */ +- enetc_mdio_wr(hw, MDIO_DATA, MDIO_DATA(value)); ++ enetc_mdio_wr(mdio_priv, MDIO_DATA, MDIO_DATA(value)); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + +@@ -93,7 +103,6 @@ int enetc_mdio_write(struct mii_bus *bus + int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum) + { + struct enetc_mdio_priv *mdio_priv = bus->priv; +- struct enetc_hw *hw = mdio_priv->hw; + u32 mdio_ctl, mdio_cfg; + u16 dev_addr, value; + int ret; +@@ -107,41 +116,41 @@ int enetc_mdio_read(struct mii_bus *bus, + mdio_cfg &= ~MDIO_CFG_ENC45; + } + +- enetc_mdio_wr(hw, MDIO_CFG, mdio_cfg); ++ enetc_mdio_wr(mdio_priv, MDIO_CFG, mdio_cfg); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + + /* set port and device addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); +- enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl); ++ enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl); + + /* set the register address */ + if (regnum & MII_ADDR_C45) { +- enetc_mdio_wr(hw, MDIO_ADDR, regnum & 0xffff); ++ enetc_mdio_wr(mdio_priv, MDIO_ADDR, regnum & 0xffff); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + } + + /* initiate the read */ +- enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl | MDIO_CTL_READ); ++ enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl | MDIO_CTL_READ); + +- ret = enetc_mdio_wait_complete(hw); ++ ret = enetc_mdio_wait_complete(mdio_priv); + if (ret) + return ret; + + /* return all Fs if nothing was there */ +- if (enetc_mdio_rd(hw, MDIO_CFG) & MDIO_CFG_RD_ER) { ++ if (enetc_mdio_rd(mdio_priv, MDIO_CFG) & MDIO_CFG_RD_ER) { + dev_dbg(&bus->dev, + "Error while reading PHY%d reg at %d.%hhu\n", + phy_id, dev_addr, regnum); + return 0xffff; + } + +- value = enetc_mdio_rd(hw, MDIO_DATA) & 0xffff; ++ value = enetc_mdio_rd(mdio_priv, MDIO_DATA) & 0xffff; + + return value; + } +@@ -164,6 +173,7 @@ int enetc_mdio_probe(struct enetc_pf *pf + bus->parent = dev; + mdio_priv = bus->priv; + mdio_priv->hw = &pf->si->hw; ++ mdio_priv->mdio_base = ENETC_EMDIO_BASE; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + + np = of_get_child_by_name(dev->of_node, "mdio"); +--- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.h ++++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.h +@@ -2,10 +2,10 @@ + /* Copyright 2019 NXP */ + + #include <linux/phy.h> +-#include "enetc_pf.h" + + struct enetc_mdio_priv { + struct enetc_hw *hw; ++ int mdio_base; + }; + + int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value); +--- a/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c ++++ b/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c +@@ -1,6 +1,7 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + /* Copyright 2019 NXP */ + #include <linux/of_mdio.h> ++#include "enetc_pf.h" + #include "enetc_mdio.h" + + #define ENETC_MDIO_DEV_ID 0xee01 +@@ -31,6 +32,7 @@ static int enetc_pci_mdio_probe(struct p + bus->parent = dev; + mdio_priv = bus->priv; + mdio_priv->hw = hw; ++ mdio_priv->mdio_base = ENETC_EMDIO_BASE; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + + pcie_flr(pdev); |